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[67.52.129.61]) by mx.google.com with ESMTPSA id fn4sm639997pab.39.2014.10.08.11.26.03 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 08 Oct 2014 11:26:03 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 8 Oct 2014 13:25:43 -0500 Message-Id: <1412792743-30906-2-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412792743-30906-1-git-send-email-greg.bellows@linaro.org> References: <1412792743-30906-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.48 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH] target-arm: add second UART to virt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.51 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Added UART1 to virt to enable separate UARTs for secure/nonsecure worlds. Signed-off-by: Greg Bellows --- hw/arm/virt.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 8c6b171..0740cdc 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -64,7 +64,8 @@ enum { VIRT_CPUPERIPHS, VIRT_GIC_DIST, VIRT_GIC_CPU, - VIRT_UART, + VIRT_UART0, + VIRT_UART1, VIRT_MMIO, VIRT_RTC, }; @@ -104,8 +105,9 @@ static const MemMapEntry a15memmap[] = { /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, - [VIRT_UART] = { 0x09000000, 0x00001000 }, - [VIRT_RTC] = { 0x09010000, 0x00001000 }, + [VIRT_UART0] = { 0x09000000, 0x00001000 }, + [VIRT_UART1] = { 0x09010000, 0x00001000 }, + [VIRT_RTC] = { 0x09020000, 0x00001000 }, [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ /* 0x10000000 .. 0x40000000 reserved for PCI */ @@ -113,8 +115,9 @@ static const MemMapEntry a15memmap[] = { }; static const int a15irqmap[] = { - [VIRT_UART] = 1, - [VIRT_RTC] = 2, + [VIRT_UART0] = 1, + [VIRT_UART1] = 2, + [VIRT_RTC] = 3, [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ }; @@ -352,12 +355,12 @@ static void create_gic(const VirtBoardInfo *vbi, qemu_irq *pic) fdt_add_gic_node(vbi); } -static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic) +static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic, int uart) { char *nodename; - hwaddr base = vbi->memmap[VIRT_UART].base; - hwaddr size = vbi->memmap[VIRT_UART].size; - int irq = vbi->irqmap[VIRT_UART]; + hwaddr base = vbi->memmap[uart].base; + hwaddr size = vbi->memmap[uart].size; + int irq = vbi->irqmap[uart]; const char compat[] = "arm,pl011\0arm,primecell"; const char clocknames[] = "uartclk\0apb_pclk"; @@ -589,7 +592,8 @@ static void machvirt_init(MachineState *machine) create_gic(vbi, pic); - create_uart(vbi, pic); + create_uart(vbi, pic, VIRT_UART0); + create_uart(vbi, pic, VIRT_UART1); create_rtc(vbi, pic);