From patchwork Tue Sep 30 21:49:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 38213 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f197.google.com (mail-lb0-f197.google.com [209.85.217.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 177192032C for ; Tue, 30 Sep 2014 22:12:09 +0000 (UTC) Received: by mail-lb0-f197.google.com with SMTP id p9sf1545628lbv.8 for ; Tue, 30 Sep 2014 15:12:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=rJmau8OsI+tXn0fZsRLQP/AkbbcEdmGX0wqK4F16bHA=; b=KwgCStF7HezuY7w4c6qM0CDHahHIfZF0u08M2lqdbzNhNY42P0VqmX9Yrjtk4nqU0s tppY589E5L8B/2lbBdm44m8zOsngAixfDcJhgnK4NzuNAGTQRnoJAYL8Ok3EGUrzn0eI 0BA2T+bpqoilKsDFLaUobiXkrGo482HQHMfRlo/Nj2ahcHUWMwuAPGtjdnrhG8OQ/E92 YKPhwMrtu87BhDqlMBYXJCnSP6wskAGtziIodiYHcV/IX4V7hz6XG4NpvCaTPRWtt8K9 Gt9Ufud8KYcFNeYcaSsWgoBmb13f+PtFSKx/xg6by+qKJdgvglHK1KQOEcd9WLinc0jV AqXQ== X-Gm-Message-State: ALoCoQnPpSj9ZRjMSSAOrLEdprpNJpt7pBt7Xy4Xj40jLu5RtOF6GOsnC3mZHNQ/CmUBpxy9BPp5 X-Received: by 10.112.6.138 with SMTP id b10mr6969lba.18.1412115128888; Tue, 30 Sep 2014 15:12:08 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.43.103 with SMTP id v7ls100730lal.32.gmail; Tue, 30 Sep 2014 15:12:08 -0700 (PDT) X-Received: by 10.112.159.169 with SMTP id xd9mr47785694lbb.71.1412115128750; Tue, 30 Sep 2014 15:12:08 -0700 (PDT) Received: from mail-lb0-f174.google.com (mail-lb0-f174.google.com [209.85.217.174]) by mx.google.com with ESMTPS id lj3si24528504lab.102.2014.09.30.15.12.08 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 30 Sep 2014 15:12:08 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.174 as permitted sender) client-ip=209.85.217.174; Received: by mail-lb0-f174.google.com with SMTP id p9so2373949lbv.19 for ; Tue, 30 Sep 2014 15:12:08 -0700 (PDT) X-Received: by 10.152.7.73 with SMTP id h9mr18565778laa.27.1412115128185; Tue, 30 Sep 2014 15:12:08 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.130.169 with SMTP id of9csp431687lbb; Tue, 30 Sep 2014 15:12:07 -0700 (PDT) X-Received: by 10.224.63.140 with SMTP id b12mr49290200qai.22.1412115127108; Tue, 30 Sep 2014 15:12:07 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id x2si20327444qal.115.2014.09.30.15.12.06 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 30 Sep 2014 15:12:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Received: from localhost ([::1]:46820 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5eQ-0000x3-D8 for patch@linaro.org; Tue, 30 Sep 2014 18:12:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43548) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5Jy-0001Ds-I3 for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:51:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZ5Jp-00043h-Qk for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:58 -0400 Received: from mail-pa0-f42.google.com ([209.85.220.42]:46659) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5Jo-00042s-Ny for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:49 -0400 Received: by mail-pa0-f42.google.com with SMTP id et14so2542506pad.15 for ; Tue, 30 Sep 2014 14:50:44 -0700 (PDT) X-Received: by 10.68.175.99 with SMTP id bz3mr73717415pbc.112.1412113844600; Tue, 30 Sep 2014 14:50:44 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id qy1sm16027662pbc.27.2014.09.30.14.50.43 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 30 Sep 2014 14:50:43 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 30 Sep 2014 16:49:45 -0500 Message-Id: <1412113785-21525-34-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.42 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v5 33/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index ea2169b..2a0eeb3 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -601,6 +601,7 @@ static void arm1176_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fb767; cpu->reset_fpsid = 0x410120b5; cpu->mvfr0 = 0x11111111; @@ -687,6 +688,7 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fc080; cpu->reset_fpsid = 0x410330c0; cpu->mvfr0 = 0x11110222; @@ -754,6 +756,7 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). @@ -821,6 +824,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_LPAE); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1; cpu->reset_fpsid = 0x410430f0;