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[67.52.129.61]) by mx.google.com with ESMTPSA id qy1sm16027662pbc.27.2014.09.30.14.50.39 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 30 Sep 2014 14:50:39 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 30 Sep 2014 16:49:42 -0500 Message-Id: <1412113785-21525-31-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.171 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v5 30/33] target-arm: make MAIR0/1 banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Added CP register info entries for the ARMv7 MAIR0/1 secure banks. Signed-off-by: Greg Bellows --- target-arm/cpu.h | 1 + target-arm/helper.c | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 1fa9e0d..7a8eaef 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -311,6 +311,7 @@ typedef struct CPUARMState { uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; + uint64_t mair_el3; union { /* vector base address register */ struct { uint64_t _unused_vbar; diff --git a/target-arm/helper.c b/target-arm/helper.c index 8543813..e91a019 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -958,11 +958,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { */ { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, - .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1), + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.mair_el3), + offsetoflow32(CPUARMState, cp15.mair_el1) }, .resetfn = arm_cp_reset_ignore }, { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, - .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1), + .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.mair_el3), + offsetofhigh32(CPUARMState, cp15.mair_el1) }, .resetfn = arm_cp_reset_ignore }, { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,