From patchwork Tue Sep 30 21:49:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 38199 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f197.google.com (mail-wi0-f197.google.com [209.85.212.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id C525B2032C for ; Tue, 30 Sep 2014 22:01:46 +0000 (UTC) Received: by mail-wi0-f197.google.com with SMTP id ho1sf4270017wib.4 for ; Tue, 30 Sep 2014 15:01:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=mDh4QR31d7XO9q82nypY584J/SoUZaJVtnvOwL52UeU=; b=ecMWZtUaoWeyUXbJRtrGpY5w43bO4FjltUUS9z4E4vPEQcTaL5z3KCBrIudjXPwonE IRY1/N+Apu3BGZn5bK0+tMYFXiIPnCsycYRfCtiYo1OhpoiZiYUXZFeBwwMBFcAYTyxP OcYwArAhiVXdPbSf9w2CmoWX8IxvZFXyZfdyakV0azfLVPAw2pIfHCXQpKKIddoG4pKk gnDgpuwprDy9cw7xVmpgCX+hf2N+bg9w4qWD8CDvatJEdCcX41yMKnTXsNE9TpNIlRyU PEGRJy1fVLEHQrOYRkJKghrRP3nTGabksmkr6+8FHkKsa4IWg0TVEPXvhrDI9pDkoT68 PYMw== X-Gm-Message-State: ALoCoQlkot4ibhC9LaUW1Q/GpCpra2jmi4cW0YhfM/+xks3qFVZoLcoLvQ8ftnqd3eaAGSiB6/4o X-Received: by 10.152.19.131 with SMTP id f3mr7473116lae.0.1412114505939; Tue, 30 Sep 2014 15:01:45 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.18.227 with SMTP id z3ls94929lad.44.gmail; Tue, 30 Sep 2014 15:01:45 -0700 (PDT) X-Received: by 10.112.61.225 with SMTP id t1mr6428539lbr.104.1412114505801; Tue, 30 Sep 2014 15:01:45 -0700 (PDT) Received: from mail-lb0-f178.google.com (mail-lb0-f178.google.com [209.85.217.178]) by mx.google.com with ESMTPS id k1si24509851lam.96.2014.09.30.15.01.45 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 30 Sep 2014 15:01:45 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.178 as permitted sender) client-ip=209.85.217.178; Received: by mail-lb0-f178.google.com with SMTP id w7so4092794lbi.9 for ; Tue, 30 Sep 2014 15:01:45 -0700 (PDT) X-Received: by 10.152.22.137 with SMTP id d9mr51014862laf.29.1412114505724; Tue, 30 Sep 2014 15:01:45 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.130.169 with SMTP id of9csp430414lbb; Tue, 30 Sep 2014 15:01:45 -0700 (PDT) X-Received: by 10.140.101.139 with SMTP id u11mr31243418qge.48.1412114504661; Tue, 30 Sep 2014 15:01:44 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id v9si20344651qat.80.2014.09.30.15.01.44 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 30 Sep 2014 15:01:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Received: from localhost ([::1]:46624 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5UO-00010Z-2H for patch@linaro.org; Tue, 30 Sep 2014 18:01:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43139) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5JL-0000XP-Oj for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZ5JG-0003pG-2B for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:19 -0400 Received: from mail-pd0-f171.google.com ([209.85.192.171]:33872) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5JF-0003lo-RN for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:14 -0400 Received: by mail-pd0-f171.google.com with SMTP id ft15so4236401pdb.30 for ; Tue, 30 Sep 2014 14:50:07 -0700 (PDT) X-Received: by 10.68.65.99 with SMTP id w3mr23508306pbs.90.1412113807404; Tue, 30 Sep 2014 14:50:07 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id qy1sm16027662pbc.27.2014.09.30.14.50.06 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 30 Sep 2014 14:50:06 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 30 Sep 2014 16:49:21 -0500 Message-Id: <1412113785-21525-10-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.171 Cc: Sergey Fedorov , Greg Bellows Subject: [Qemu-devel] [PATCH v5 09/33] target-arm: add macros to access banked registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler If EL3 is in Aarch32 state certain cp registers are banked (secure and non-secure instance). When reading or writing to coprocessor registers the following macros can be used. - A32_BANKED macros are used for choosing the banked register based on provided input security argument. This macro is used to choose the bank during translation of MRC/MCR instructions that are dependent on something other than the current secure state. - A32_BANKED_CURRENT macros are used for choosing the banked register based on current secure state. This is NOT to be used for choosing the bank used during translation as it breaks monitor mode. If EL3 is operating in Aarch64 state coprocessor registers are not banked anymore. The macros use the non-secure instance (_ns) in this case, which is architecturally mapped to the Aarch64 EL register. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ---------- v4 -> v5 - Cleaned-up macros to try and alleviate misuse. Made A32_BANKED macros take secure arg indicator rather than relying on USE_SECURE_REG. Incorporated the A32_BANKED macros into the A32_BANKED_CURRENT. CURRENT is now the only one that automatically chooses based on current secure state. --- target-arm/cpu.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 601f8fe..c58fdf5 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -807,6 +807,42 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return arm_feature(env, ARM_FEATURE_AARCH64); } +/* Macro for determing whether to use the secure or non-secure bank of a CP + * register. When EL3 is operating in Aarch32 state, the NS-bit determines + * whether the secure instance of a cp-register should be used. + */ +#define USE_SECURE_REG(_env) ( \ + arm_feature((_env), ARM_FEATURE_EL3) && \ + !arm_el_is_aa64((_env), 3) && \ + !((_env)->cp15.scr_el3 & SCR_NS)) + +/* Macros for accessing a specified CP register bank */ +#define A32_BANKED_REG_GET(_env, _regname, _secure) \ + ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) + +#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ + do { \ + if (_secure) { \ + (_env)->cp15._regname##_s = (_val); \ + } else { \ + (_env)->cp15._regname##_ns = (_val); \ + } \ + } while (0) + +/* Macros for automatically accessing a specific CP register bank depending on + * the current secure state of the system. These macros are not intended for + * supporting instruction translation reads/writes as these are dependent + * solely on the SCR.NS bit and not the mode. + */ +#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ + A32_BANKED_REG_GET((_env), _regname, \ + ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env)))) + +#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ + A32_BANKED_REG_SET((_env), _regname, \ + ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))), \ + (_val)) + void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx); inline uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,