From patchwork Sun Sep 14 19:45:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 37397 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f198.google.com (mail-wi0-f198.google.com [209.85.212.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 9BACE21177 for ; Sun, 14 Sep 2014 19:47:54 +0000 (UTC) Received: by mail-wi0-f198.google.com with SMTP id cc10sf1512023wib.9 for ; Sun, 14 Sep 2014 12:47:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=uVGbSJg0ULL33vb3W6/wjIa5oHTd9M5WJaLvolQwLQ8=; b=isivqGL8JcgSOmOwme2Gat96TNmn0AP9G5LubfDSeaD4kVKIs2oL2ipT6YVokYrol0 5vQYBf7+1XVG0DFurwFk7bx1mv1Y8dBKJKN7Y9yRKjui88jas+YCGh2iAgnD0kRs+lLJ 4B8DWnST2Xgdj4bvYfqfHqQ/8VcPP913BphbcruL1y4LyugEa9G4z50RrdYaM/29wIz8 v6tXa+Mk3DMIxLWAslNFLzffXZ+A9C1xEStv8+oGLvBNKBdHpAsg2Sa6Z++UvLUP2vJ4 BVq/AmfmLQGal7wTP59TuRMoN05O+AQXBMQhmQGzvrKe/I5Aq54Xd5+JRo7PzvPR4nF9 U92Q== X-Gm-Message-State: ALoCoQmU9OYOgkgi3XkcYAY2oPiTl4ToxU8YfCeGvrDzgxzqlFTH1uYJmMtPos3ROPtRrUTSwzvy X-Received: by 10.152.44.227 with SMTP id h3mr6116563lam.2.1410724073755; Sun, 14 Sep 2014 12:47:53 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.22.130 with SMTP id d2ls261398laf.98.gmail; Sun, 14 Sep 2014 12:47:53 -0700 (PDT) X-Received: by 10.152.43.201 with SMTP id y9mr23850539lal.54.1410724073298; Sun, 14 Sep 2014 12:47:53 -0700 (PDT) Received: from mail-la0-f48.google.com (mail-la0-f48.google.com [209.85.215.48]) by mx.google.com with ESMTPS id kf3si16154895lbc.68.2014.09.14.12.47.53 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 14 Sep 2014 12:47:53 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) client-ip=209.85.215.48; Received: by mail-la0-f48.google.com with SMTP id ty20so3494707lab.7 for ; Sun, 14 Sep 2014 12:47:53 -0700 (PDT) X-Received: by 10.112.76.6 with SMTP id g6mr22219973lbw.22.1410724073190; Sun, 14 Sep 2014 12:47:53 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.112.130.169 with SMTP id of9csp113851lbb; Sun, 14 Sep 2014 12:47:52 -0700 (PDT) X-Received: by 10.70.45.41 with SMTP id j9mr37514607pdm.85.1410724070760; Sun, 14 Sep 2014 12:47:50 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id xl6si19289991pab.225.2014.09.14.12.47.49 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 14 Sep 2014 12:47:50 -0700 (PDT) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=81.2.115.146; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XTFju-0004h5-G6; Sun, 14 Sep 2014 20:45:38 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Aurelien Jarno , Richard Henderson Subject: [PATCH 3/5] target-mips/dsp_helper.c: Add ifdef guards around various functions Date: Sun, 14 Sep 2014 20:45:36 +0100 Message-Id: <1410723938-18007-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1410723938-18007-1-git-send-email-peter.maydell@linaro.org> References: <1410723938-18007-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add ifdef TARGET_MIPS64 guards around various functions that are only called from helpers for TARGET_MIPS64 CPUs; this avoids compiler warnings when building other configs. Signed-off-by: Peter Maydell --- target-mips/dsp_helper.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 94083fb..09fb470 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -283,6 +283,7 @@ static inline int32_t mipsdsp_sat32_acc_q31(int32_t acc, int32_t a, return result; } +#ifdef TARGET_MIPS64 /* a[0] is LO, a[1] is HI. */ static inline void mipsdsp_sat64_acc_add_q63(int64_t *ret, int32_t ac, @@ -336,6 +337,7 @@ static inline void mipsdsp_sat64_acc_sub_q63(int64_t *ret, set_DSPControl_overflow_flag(1, 16 + ac, env); } } +#endif static inline int32_t mipsdsp_mul_i16_i16(int16_t a, int16_t b, CPUMIPSState *env) @@ -357,10 +359,12 @@ static inline int32_t mipsdsp_mul_u16_u16(int32_t a, int32_t b) return a * b; } +#ifdef TARGET_MIPS64 static inline int32_t mipsdsp_mul_i32_i32(int32_t a, int32_t b) { return a * b; } +#endif static inline int32_t mipsdsp_sat16_mul_i16_i16(int16_t a, int16_t b, CPUMIPSState *env) @@ -417,10 +421,12 @@ static inline int16_t mipsdsp_rashift16(int16_t a, target_ulong mov) return a >> mov; } +#ifdef TARGET_MIPS64 static inline int32_t mipsdsp_rashift32(int32_t a, target_ulong mov) { return a >> mov; } +#endif static inline int16_t mipsdsp_rshift1_add_q16(int16_t a, int16_t b) { @@ -479,6 +485,7 @@ static inline uint8_t mipsdsp_rrshift1_add_u8(uint8_t a, uint8_t b) return (temp >> 1) & 0x00FF; } +#ifdef TARGET_MIPS64 static inline uint8_t mipsdsp_rshift1_sub_u8(uint8_t a, uint8_t b) { uint16_t temp; @@ -496,6 +503,7 @@ static inline uint8_t mipsdsp_rrshift1_sub_u8(uint8_t a, uint8_t b) return (temp >> 1) & 0x00FF; } +#endif /* 128 bits long. p[0] is LO, p[1] is HI. */ static inline void mipsdsp_rndrashift_short_acc(int64_t *p, @@ -511,6 +519,7 @@ static inline void mipsdsp_rndrashift_short_acc(int64_t *p, p[1] = (acc >> 63) & 0x01; } +#ifdef TARGET_MIPS64 /* 128 bits long. p[0] is LO, p[1] is HI */ static inline void mipsdsp_rashift_acc(uint64_t *p, uint32_t ac, @@ -558,6 +567,7 @@ static inline void mipsdsp_rndrashift_acc(uint64_t *p, } } } +#endif static inline int32_t mipsdsp_mul_q15_q15(int32_t ac, uint16_t a, uint16_t b, CPUMIPSState *env) @@ -608,10 +618,12 @@ static inline uint16_t mipsdsp_mul_u8_u16(uint8_t a, uint16_t b, return tempI & 0x0000FFFF; } +#ifdef TARGET_MIPS64 static inline uint64_t mipsdsp_mul_u32_u32(uint32_t a, uint32_t b) { return (uint64_t)a * (uint64_t)b; } +#endif static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a, uint16_t b, CPUMIPSState *env) @@ -717,7 +729,7 @@ static inline uint16_t mipsdsp_lshift16(uint16_t a, uint8_t s, return a << s; } - +#ifdef TARGET_MIPS64 static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s, CPUMIPSState *env) { @@ -734,6 +746,7 @@ static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s, return a << s; } } +#endif static inline uint16_t mipsdsp_sat16_lshift(uint16_t a, uint8_t s, CPUMIPSState *env) @@ -973,6 +986,7 @@ static inline uint8_t mipsdsp_satu8_sub(uint8_t a, uint8_t b, CPUMIPSState *env) return temp & 0x00FF; } +#ifdef TARGET_MIPS64 static inline uint32_t mipsdsp_sub32(int32_t a, int32_t b, CPUMIPSState *env) { int32_t temp; @@ -997,6 +1011,7 @@ static inline int32_t mipsdsp_add_i32(int32_t a, int32_t b, CPUMIPSState *env) return temp; } +#endif static inline int32_t mipsdsp_cmp_eq(int32_t a, int32_t b) {