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[81.2.115.146]) by mx.google.com with ESMTPS id nr9si19320490pdb.206.2014.09.14.12.46.46 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 14 Sep 2014 12:46:47 -0700 (PDT) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=81.2.115.146; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XTFju-0004h1-Ey; Sun, 14 Sep 2014 20:45:38 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Aurelien Jarno , Richard Henderson Subject: [PATCH 2/5] target-mips/translate.c: Add ifdef guard around check_mips64() Date: Sun, 14 Sep 2014 20:45:35 +0100 Message-Id: <1410723938-18007-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1410723938-18007-1-git-send-email-peter.maydell@linaro.org> References: <1410723938-18007-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The function check_mips64() is only used if TARGET_MIPS64 is defined; add an ifdef guard to its definition to avoid warnings about it being unused in other configurations. Signed-off-by: Peter Maydell --- target-mips/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index 2ce9fed..b3a2a37 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1421,6 +1421,7 @@ static inline void check_insn(DisasContext *ctx, int flags) } } +#ifdef TARGET_MIPS64 /* This code generates a "reserved instruction" exception if 64-bit instructions are not enabled. */ static inline void check_mips_64(DisasContext *ctx) @@ -1428,6 +1429,7 @@ static inline void check_mips_64(DisasContext *ctx) if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) generate_exception(ctx, EXCP_RI); } +#endif /* Define small wrappers for gen_load_fpr* so that we have a uniform calling interface for 32 and 64-bit FPRs. No sense in changing