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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id i60si347406qge.60.2014.08.29.07.43.14 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 29 Aug 2014 07:43:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:42371 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XNNOU-0007ND-BK for patch@linaro.org; Fri, 29 Aug 2014 10:43:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49840) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XNNJ6-00077f-6t for qemu-devel@nongnu.org; Fri, 29 Aug 2014 10:37:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XNNIy-00082a-8v for qemu-devel@nongnu.org; Fri, 29 Aug 2014 10:37:39 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:46762) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XNNIy-000805-2H for qemu-devel@nongnu.org; Fri, 29 Aug 2014 10:37:32 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XNNIv-00051p-Hk for qemu-devel@nongnu.org; Fri, 29 Aug 2014 15:37:29 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 29 Aug 2014 15:37:22 +0100 Message-Id: <1409323049-19255-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1409323049-19255-1-git-send-email-peter.maydell@linaro.org> References: <1409323049-19255-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 81.2.115.146 Subject: [Qemu-devel] [PULL 10/16] target-arm: Make the ARM PMCCNTR register 64-bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Alistair Francis This makes the PMCCNTR register 64-bit to allow for the 64-bit ARMv8 version. Signed-off-by: Peter Crosthwaite Signed-off-by: Alistair Francis Message-id: 6c5bac5fd0ea54963b1fc0e7f9464909f2e19a73.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- target-arm/cpu.h | 2 +- target-arm/helper.c | 19 +++++++++---------- 2 files changed, 10 insertions(+), 11 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 659b104..986c249 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -224,7 +224,7 @@ typedef struct CPUARMState { /* If the counter is enabled, this stores the last time the counter * was reset. Otherwise it stores the counter value */ - uint32_t c15_ccnt; + uint64_t c15_ccnt; } cp15; struct { diff --git a/target-arm/helper.c b/target-arm/helper.c index 2a77c97..711ca12 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -551,11 +551,10 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri) static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Don't computer the number of ticks in user mode */ - uint32_t temp_ticks; + uint64_t temp_ticks; - temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * - get_ticks_per_sec() / 1000000; + temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), + get_ticks_per_sec(), 1000000); if (env->cp15.c9_pmcr & PMCRE) { /* If the counter is enabled */ @@ -587,15 +586,15 @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - uint32_t total_ticks; + uint64_t total_ticks; if (!(env->cp15.c9_pmcr & PMCRE)) { /* Counter is disabled, do not change value */ return env->cp15.c15_ccnt; } - total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * - get_ticks_per_sec() / 1000000; + total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), + get_ticks_per_sec(), 1000000); if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ @@ -607,7 +606,7 @@ static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - uint32_t total_ticks; + uint64_t total_ticks; if (!(env->cp15.c9_pmcr & PMCRE)) { /* Counter is disabled, set the absolute value */ @@ -615,8 +614,8 @@ static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, return; } - total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * - get_ticks_per_sec() / 1000000; + total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), + get_ticks_per_sec(), 1000000); if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */