From patchwork Fri Aug 29 11:21:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 36514 Delivered-To: patches@linaro.org Received: by 10.221.45.67 with SMTP id uj3csp22vcb; Fri, 29 Aug 2014 04:22:39 -0700 (PDT) X-Received: by 10.180.101.129 with SMTP id fg1mr3196992wib.20.1409311359351; Fri, 29 Aug 2014 04:22:39 -0700 (PDT) Return-Path: Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id l3si11863572wjy.97.2014.08.29.04.22.38 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 29 Aug 2014 04:22:39 -0700 (PDT) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=neutral (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XNKFI-0004v3-EG; Fri, 29 Aug 2014 12:21:32 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paolo Bonzini , Richard Henderson Subject: [PATCH 06/10] target-arm: Move extended_addresses_enabled() to internals.h Date: Fri, 29 Aug 2014 12:21:28 +0100 Message-Id: <1409311292-18860-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1409311292-18860-1-git-send-email-peter.maydell@linaro.org> References: <1409311292-18860-1-git-send-email-peter.maydell@linaro.org> Move the utility function extended_addresses_enabled() into internals.h; we're going to need to call it from op_helper.c. Signed-off-by: Peter Maydell --- target-arm/helper.c | 11 ----------- target-arm/internals.h | 11 +++++++++++ 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 406b9bc..7963807 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -304,17 +304,6 @@ void init_cpreg_list(ARMCPU *cpu) g_list_free(keys); } -/* Return true if extended addresses are enabled. - * This is always the case if our translation regime is 64 bit, - * but depends on TTBCR.EAE for 32 bit. - */ -static inline bool extended_addresses_enabled(CPUARMState *env) -{ - return arm_el_is_aa64(env, 1) - || ((arm_feature(env, ARM_FEATURE_LPAE) - && (env->cp15.c2_control & TTBCR_EAE))); -} - static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = arm_env_get_cpu(env); diff --git a/target-arm/internals.h b/target-arm/internals.h index 22f382c..1d788b0 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -142,6 +142,17 @@ static inline void update_spsel(CPUARMState *env, uint32_t imm) aarch64_restore_sp(env, cur_el); } +/* Return true if extended addresses are enabled. + * This is always the case if our translation regime is 64 bit, + * but depends on TTBCR.EAE for 32 bit. + */ +static inline bool extended_addresses_enabled(CPUARMState *env) +{ + return arm_el_is_aa64(env, 1) + || ((arm_feature(env, ARM_FEATURE_LPAE) + && (env->cp15.c2_control & TTBCR_EAE))); +} + /* Valid Syndrome Register EC field values */ enum arm_exception_class { EC_UNCATEGORIZED = 0x00,