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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id o106si9777852qgd.76.2014.08.29.04.24.01 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 29 Aug 2014 04:24:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:41388 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XNKHg-0000NQ-Vn for patch@linaro.org; Fri, 29 Aug 2014 07:24:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38037) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XNKGa-0007eC-Sb for qemu-devel@nongnu.org; Fri, 29 Aug 2014 07:22:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XNKGU-00072m-31 for qemu-devel@nongnu.org; Fri, 29 Aug 2014 07:22:52 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:46718) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XNKGT-00070y-TE for qemu-devel@nongnu.org; Fri, 29 Aug 2014 07:22:46 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XNKFI-0004ur-9V; Fri, 29 Aug 2014 12:21:32 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 29 Aug 2014 12:21:25 +0100 Message-Id: <1409311292-18860-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1409311292-18860-1-git-send-email-peter.maydell@linaro.org> References: <1409311292-18860-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 81.2.115.146 Cc: Paolo Bonzini , Richard Henderson , =?UTF-8?q?Andreas=20F=C3=A4rber?= , patches@linaro.org Subject: [Qemu-devel] [PATCH 03/10] exec.c: Record watchpoint fault address and direction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 When we check whether we've hit a watchpoint we know the address that we were attempting to access and whether it was a read or a write. Record this information in the CPUWatchpoint struct so that target-specific code can report it to the guest. Signed-off-by: Peter Maydell --- exec.c | 7 ++++++- include/qom/cpu.h | 6 +++++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/exec.c b/exec.c index 82a90e7..57376c0 100644 --- a/exec.c +++ b/exec.c @@ -1638,7 +1638,12 @@ static void check_watchpoint(int offset, int len, int flags) QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (cpu_watchpoint_address_matches(wp, vaddr, len) && (wp->flags & flags)) { - wp->flags |= BP_WATCHPOINT_HIT; + if (flags == BP_MEM_READ) { + wp->flags |= BP_WATCHPOINT_HIT_READ; + } else { + wp->flags |= BP_WATCHPOINT_HIT_WRITE; + } + wp->hitaddr = vaddr; if (!cpu->watchpoint_hit) { cpu->watchpoint_hit = wp; tb_check_watchpoint(cpu); diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 7c06f37..c325774 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -170,6 +170,7 @@ typedef struct CPUBreakpoint { typedef struct CPUWatchpoint { vaddr vaddr; vaddr len; + vaddr hitaddr; int flags; /* BP_* */ QTAILQ_ENTRY(CPUWatchpoint) entry; } CPUWatchpoint; @@ -622,9 +623,12 @@ void cpu_single_step(CPUState *cpu, int enabled); #define BP_MEM_WRITE 0x02 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) #define BP_STOP_BEFORE_ACCESS 0x04 -#define BP_WATCHPOINT_HIT 0x08 +/* 0x08 currently unused */ #define BP_GDB 0x10 #define BP_CPU 0x20 +#define BP_WATCHPOINT_HIT_READ 0x40 +#define BP_WATCHPOINT_HIT_WRITE 0x80 +#define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, CPUBreakpoint **breakpoint);