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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id a18si30091186qgf.104.2014.08.19.11.12.19 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 19 Aug 2014 11:12:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:52399 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XJntL-0002NC-JD for patch@linaro.org; Tue, 19 Aug 2014 14:12:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50421) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XJns6-00016I-4N for qemu-devel@nongnu.org; Tue, 19 Aug 2014 14:11:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XJnrz-00043K-MN for qemu-devel@nongnu.org; Tue, 19 Aug 2014 14:11:02 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:42051) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XJnrz-0003wv-Gg for qemu-devel@nongnu.org; Tue, 19 Aug 2014 14:10:55 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XJnqr-0000iR-3U for qemu-devel@nongnu.org; Tue, 19 Aug 2014 19:09:45 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 19 Aug 2014 19:09:40 +0100 Message-Id: <1408471784-2652-16-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1408471784-2652-1-git-send-email-peter.maydell@linaro.org> References: <1408471784-2652-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 81.2.115.146 Subject: [Qemu-devel] [PULL 15/19] arm: cortex-a9: Fix cache-line size and associativity X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Peter Crosthwaite For A9, The cache associativity is 4 and the lines size is 32B. Self identify in CCSIDR accordingly. Cache size remains at 16k. QEMU doesn't emulate caches, but we should still report the correct cache-line size to the guest. Some guests (like u-boot) complain if the cache-line size mismatches a requested flush or invalidate operation. Signed-off-by: Peter Crosthwaite Message-id: 1de6bd40155a1d2f2e93e24b1b1d1d677a432641.1408346233.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- target-arm/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index e27cca2..8199f32 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -715,8 +715,8 @@ static void cortex_a9_initfn(Object *obj) cpu->id_isar4 = 0x00111142; cpu->dbgdidr = 0x35141000; cpu->clidr = (1 << 27) | (1 << 24) | 3; - cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ - cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ + cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ + cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ define_arm_cp_regs(cpu, cortexa9_cp_reginfo); }