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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id i10si16259488qcc.28.2014.08.01.09.10.14 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 01 Aug 2014 09:10:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:40470 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XDFPJ-00029U-QG for patch@linaro.org; Fri, 01 Aug 2014 12:10:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58915) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XDFOB-0000uz-4w for qemu-devel@nongnu.org; Fri, 01 Aug 2014 12:09:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XDFO2-00058t-RW for qemu-devel@nongnu.org; Fri, 01 Aug 2014 12:09:03 -0400 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:56654 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XDFO2-00058X-Ku for qemu-devel@nongnu.org; Fri, 01 Aug 2014 12:08:54 -0400 Received: from localhost ([127.0.0.1] helo=zen.linaro.local) by socrates.bennee.com with esmtp (Exim 4.80) (envelope-from ) id 1XDFYA-0004QQ-7w; Fri, 01 Aug 2014 18:19:22 +0200 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: stefanha@redhat.com Date: Fri, 1 Aug 2014 17:08:57 +0100 Message-Id: <1406909337-32224-3-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.0.3 In-Reply-To: <1406909337-32224-1-git-send-email-alex.bennee@linaro.org> References: <1406909337-32224-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 127.0.0.1 X-SA-Exim-Mail-From: alex.bennee@linaro.org X-SA-Exim-Scanned: No (on socrates.bennee.com); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 88.198.71.155 Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH v4 2/2] trace: add some tcg tracing support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: alex.bennee@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.182 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This adds a couple of tcg specific trace-events which are useful for tracing execution though tcg generated blocks. It's been tested with lttng user space tracing but is generic enough for all systems. The tcg events are: * translate_block - when a subject block is translated * exec_tb - when a translated block is entered * exec_tb_exit - when we exit the translated code * exec_tb_nocache - special case translations Of course we can only trace the entrance to the first block of a chain as each block will jump directly to the next when it can. See the -d nochain patch to allow more complete tracing at the expense of performance. Signed-off-by: Alex Bennée --- v2 - rebase v3: - checkpatch clean-ups - add sign-off - disable exec_tb by default v4: - fix fmt strings for uintptr_t diff --git a/cpu-exec.c b/cpu-exec.c index 38e5f02..d209568 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -18,6 +18,7 @@ */ #include "config.h" #include "cpu.h" +#include "trace.h" #include "disas/disas.h" #include "tcg.h" #include "qemu/atomic.h" @@ -65,6 +66,9 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr) #endif /* DEBUG_DISAS */ next_tb = tcg_qemu_tb_exec(env, tb_ptr); + trace_exec_tb_exit((void *) (next_tb & ~TB_EXIT_MASK), + next_tb & TB_EXIT_MASK); + if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) { /* We didn't start executing this TB (eg because the instruction * counter hit zero); we must restore the guest PC to the address @@ -105,6 +109,7 @@ static void cpu_exec_nocache(CPUArchState *env, int max_cycles, max_cycles); cpu->current_tb = tb; /* execute the generated code */ + trace_exec_tb_nocache(tb, tb->pc); cpu_tb_exec(cpu, tb->tc_ptr); cpu->current_tb = NULL; tb_phys_invalidate(tb, -1); @@ -637,6 +642,7 @@ int cpu_exec(CPUArchState *env) cpu->current_tb = tb; barrier(); if (likely(!cpu->exit_request)) { + trace_exec_tb(tb, tb->pc); tc_ptr = tb->tc_ptr; /* execute the generated code */ next_tb = cpu_tb_exec(cpu, tc_ptr); diff --git a/trace-events b/trace-events index 11a17a8..dcc33dd 100644 --- a/trace-events +++ b/trace-events @@ -1265,6 +1265,15 @@ kvm_failed_spr_get(int str, const char *msg) "Warning: Unable to retrieve SPR %d kvm_failed_reg_get(uint64_t id, const char *msg) "Warning: Unable to retrieve ONEREG %" PRIu64 " from KVM: %s" kvm_failed_reg_set(uint64_t id, const char *msg) "Warning: Unable to set ONEREG %" PRIu64 " to KVM: %s" +# TCG related tracing (mostly disabled by default) +# cpu-exec.c +disable exec_tb(void *tb, uintptr_t pc) "tb:%p pc=0x%"PRIxPTR +disable exec_tb_nocache(void *tb, uintptr_t pc) "tb:%p pc=0x%"PRIxPTR +disable exec_tb_exit(void *next_tb, unsigned int flags) "tb:%p flags=%x" + +# translate-all.c +translate_block(void *tb, uintptr_t pc, uint8_t *tb_code) "tb:%p, pc:0x%"PRIxPTR", tb_code:%p" + # memory.c memory_region_ops_read(void *mr, uint64_t addr, uint64_t value, unsigned size) "mr %p addr %#"PRIx64" value %#"PRIx64" size %u" memory_region_ops_write(void *mr, uint64_t addr, uint64_t value, unsigned size) "mr %p addr %#"PRIx64" value %#"PRIx64" size %u" diff --git a/translate-all.c b/translate-all.c index 8f7e11b..2e0265a 100644 --- a/translate-all.c +++ b/translate-all.c @@ -33,6 +33,7 @@ #include "qemu-common.h" #define NO_CPU_IO_DEFS #include "cpu.h" +#include "trace.h" #include "disas/disas.h" #include "tcg.h" #if defined(CONFIG_USER_ONLY) @@ -158,6 +159,8 @@ int cpu_gen_code(CPUArchState *env, TranslationBlock *tb, int *gen_code_size_ptr gen_intermediate_code(env, tb); + trace_translate_block(tb, tb->pc, tb->tc_ptr); + /* generate machine code */ gen_code_buf = tb->tc_ptr; tb->tb_next_offset[0] = 0xffff;