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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id n7si11677696qag.73.2014.07.24.08.54.04 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 24 Jul 2014 08:54:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:50597 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XALLI-0002v4-3X for patch@linaro.org; Thu, 24 Jul 2014 11:54:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39523) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XALJK-0000Ze-Kd for qemu-devel@nongnu.org; Thu, 24 Jul 2014 11:52:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XALJF-0008Q6-Pr for qemu-devel@nongnu.org; Thu, 24 Jul 2014 11:52:02 -0400 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:60882 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XALJF-0008Pu-KX for qemu-devel@nongnu.org; Thu, 24 Jul 2014 11:51:57 -0400 Received: from localhost ([127.0.0.1] helo=zen.linaro.local) by socrates.bennee.com with esmtp (Exim 4.80) (envelope-from ) id 1XALRS-00022u-4T; Thu, 24 Jul 2014 18:00:26 +0200 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Thu, 24 Jul 2014 16:52:55 +0100 Message-Id: <1406217175-30267-4-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.0.2 In-Reply-To: <1406217175-30267-1-git-send-email-alex.bennee@linaro.org> References: <1406217175-30267-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 127.0.0.1 X-SA-Exim-Mail-From: alex.bennee@linaro.org X-SA-Exim-Scanned: No (on socrates.bennee.com); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 88.198.71.155 Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , rth@twiddle.net Subject: [Qemu-devel] [PATCH 3/3] target-arm: A64: fix use 12 bit page tables for aarch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: alex.bennee@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The aarch64 architecture only support 4k+ pages so using a smaller value for QEMU's internal page table handling only makes us less efficient. Signed-off-by: Alex Bennée diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c83f249..33359b9 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1051,11 +1051,18 @@ bool write_cpustate_to_list(ARMCPU *cpu); #if defined(CONFIG_USER_ONLY) #define TARGET_PAGE_BITS 12 #else -/* The ARM MMU allows 1k pages. */ -/* ??? Linux doesn't actually use these, and they're deprecated in recent - architecture revisions. Maybe a configure option to disable them. */ +#if defined(TARGET_AARCH64) +/* You can't configure 1k pages on aarch64 hardware */ +#define TARGET_PAGE_BITS 12 +#else +/* The ARM MMU allows 1k pages - although they are not used by Linux + * FIXME?: they're deprecated in recent architecture revisions and + * this does create a performance hit. Maybe a configure option to + * disable them? + */ #define TARGET_PAGE_BITS 10 #endif +#endif #if defined(TARGET_AARCH64) # define TARGET_PHYS_ADDR_SPACE_BITS 48