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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id g6si154634qgg.20.2014.07.10.12.36.59 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 10 Jul 2014 12:37:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:38654 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X5GcL-00021A-2S for patch@linaro.org; Thu, 10 Jul 2014 11:50:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50525) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X5GbI-0001MR-50 for qemu-devel@nongnu.org; Thu, 10 Jul 2014 11:49:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X5GbC-0006x2-45 for qemu-devel@nongnu.org; Thu, 10 Jul 2014 11:49:36 -0400 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:35641 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X5GbB-0006wx-SZ for qemu-devel@nongnu.org; Thu, 10 Jul 2014 11:49:30 -0400 Received: from localhost ([127.0.0.1] helo=zen.linaro.local) by socrates.bennee.com with esmtp (Exim 4.80) (envelope-from ) id 1X5Gg2-0007L4-Ep; Thu, 10 Jul 2014 17:54:30 +0200 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Thu, 10 Jul 2014 16:49:58 +0100 Message-Id: <1405007407-23549-2-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1405007407-23549-1-git-send-email-alex.bennee@linaro.org> References: <1405007407-23549-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 127.0.0.1 X-SA-Exim-Mail-From: alex.bennee@linaro.org X-SA-Exim-Scanned: No (on socrates.bennee.com); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 88.198.71.155 Cc: Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [Qemu-devel] [PATCH v2 01/10] target-arm/cpu.h: document various program state functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: alex.bennee@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 We have a number of program state saving functions (pstate, cpsr, xpsr) which are dependant on the mode the CPU is in. This commit adds a little documentation to each function and asserts to defend against incorrect use. Signed-off-by: Alex Bennée --- v2: - remove xpsr_state asserts diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 369d472..c2312d0 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -475,22 +475,34 @@ int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, #define PSTATE_MODE_EL1t 4 #define PSTATE_MODE_EL0t 0 -/* Return the current PSTATE value. For the moment we don't support 32<->64 bit - * interprocessing, so we don't attempt to sync with the cpsr state used by - * the 32 bit decoder. +/* ARMv8 ARM D1.7 Process state, PSTATE + * + * 31 28 27 24 23 22 21 20 22 21 20 19 16 15 8 7 5 4 0 + * +------+------+-------+-----+--------+---+------+------+-----+------+ + * | NZCV | DAIF | SS IL | EL | nRW SP | Q | GE | IT | JTE | Mode | + * +------+------+-------+-----+--------+---+------+------+-----+------+ + * + * The PSTATE is an abstraction of a number of Return the current + * PSTATE value. This is only valid for A64 hardware although can be + * read when in AArch32 mode. */ static inline uint32_t pstate_read(CPUARMState *env) { int ZF; + g_assert(is_a64(env)); + ZF = (env->ZF == 0); return (env->NF & 0x80000000) | (ZF << 30) | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | env->pstate | env->daif; } +/* Update the current PSTATE value. This doesn't include nRW which is */ static inline void pstate_write(CPUARMState *env, uint32_t val) { + g_assert(is_a64(env)); + env->ZF = (~val) & PSTATE_Z; env->NF = val; env->CF = (val >> 29) & 1; @@ -499,15 +511,22 @@ static inline void pstate_write(CPUARMState *env, uint32_t val) env->pstate = val & ~CACHED_PSTATE_BITS; } -/* Return the current CPSR value. */ +/* ARMv7-AR ARM B1.3.3 Current Program Status Register, CPSR + * + * Unlike the above PSTATE implementation these functions will attempt + * to switch processor mode when the M[4:0] bits are set. + */ uint32_t cpsr_read(CPUARMState *env); /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask); -/* Return the current xPSR value. */ +/* ARMv7-M ARM B1.4.2, special purpose program status register xPSR */ static inline uint32_t xpsr_read(CPUARMState *env) { int ZF; + + g_assert(!is_a64(env)); + ZF = (env->ZF == 0); return (env->NF & 0x80000000) | (ZF << 30) | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) @@ -519,6 +538,8 @@ static inline uint32_t xpsr_read(CPUARMState *env) /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) { + g_assert(!is_a64(env)); + if (mask & CPSR_NZCV) { env->ZF = (~val) & CPSR_Z; env->NF = val; diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 2b4ce6a..ec1fef5 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -506,8 +506,8 @@ void aarch64_cpu_do_interrupt(CPUState *cs) env->condexec_bits = 0; } - pstate_write(env, PSTATE_DAIF | PSTATE_MODE_EL1h); env->aarch64 = 1; + pstate_write(env, PSTATE_DAIF | PSTATE_MODE_EL1h); env->pc = addr; cs->interrupt_request |= CPU_INTERRUPT_EXITTB;