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[99.179.1.128]) by mx.google.com with ESMTPSA id cu7sm76370192oec.12.2014.06.30.16.10.22 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 16:10:23 -0700 (PDT) From: greg.bellows@linaro.org To: qemu-devel@nongnu.org Date: Mon, 30 Jun 2014 18:09:02 -0500 Message-Id: <1404169773-20264-3-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.219.54 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Sergey Fedorov , Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 02/33] target-arm: move Aarch32 SCR into security reglist X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Define a new ARM CP register info list for the ARMv7 Security Extension feature. Register that list only for ARM cores with Security Extension/EL3 support. Moving Aarch32 SCR into Security Extension register group. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ------------------ v3 -> v4 - Renamed security_cp_reginfo to v7_el3_cp_reginfo - Conditionalized define on whether v7 or v8 were enabled Signed-off-by: Greg Bellows Reviewed-by: Edgar E. Iglesias --- target-arm/helper.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 7c4b801..1ea30fe 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -792,9 +792,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), .resetvalue = 0 }, - { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), - .resetvalue = 0, }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, @@ -2227,6 +2224,13 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo v7_el3_cp_reginfo[] = { + { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), + .resetvalue = 0, }, + REGINFO_SENTINEL +}; + static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2489,7 +2493,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } if (arm_feature(env, ARM_FEATURE_EL3)) { - define_arm_cp_regs(cpu, v8_el3_cp_reginfo); + if (arm_feature(env, ARM_FEATURE_V8)) { + define_arm_cp_regs(cpu, v8_el3_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_V7)) { + define_arm_cp_regs(cpu, v7_el3_cp_reginfo); + } } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new