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[99.179.1.128]) by mx.google.com with ESMTPSA id cu7sm76370192oec.12.2014.06.30.16.11.14 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 16:11:15 -0700 (PDT) From: greg.bellows@linaro.org To: qemu-devel@nongnu.org Date: Mon, 30 Jun 2014 18:09:25 -0500 Message-Id: <1404169773-20264-26-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.219.45 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 25/33] target-arm: make c2_mask and c2_base_mask banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Since TTBCR is banked we will bank c2_mask and c2_base_mask too. This avoids recalculating them on switches from secure to non-secure world. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 10 ++++++++-- target-arm/helper.c | 15 +++++++++------ 2 files changed, 17 insertions(+), 8 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 35291a6..367665e 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -232,8 +232,14 @@ typedef struct CPUARMState { uint64_t tcr_el3; }; }; - uint32_t c2_mask; /* MMU translation table base selection mask. */ - uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ + struct { /* MMU translation table base selection mask. */ + uint32_t c2_mask_ns; + uint32_t c2_mask_s; + }; + struct { /* MMU translation table base 0 mask. */ + uint32_t c2_base_mask_ns; + uint32_t c2_base_mask_s; + }; uint32_t c2_data; /* MPU data cachable bits. */ uint32_t c2_insn; /* MPU instruction cachable bits. */ uint32_t c3; /* MMU domain access control register diff --git a/target-arm/helper.c b/target-arm/helper.c index 8326d1f..1006b57 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1446,8 +1446,11 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, * and the c2_mask and c2_base_mask values are meaningless. */ raw_write(env, ri, value); - env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift); - env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift); + + A32_BANKED_CURRENT_REG_SET(env, c2_mask, + ~(((uint32_t)0xffffffffu) >> maskshift)); + A32_BANKED_CURRENT_REG_SET(env, c2_base_mask, + ~((uint32_t)0x3fffu >> maskshift)); } static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1466,9 +1469,9 @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) { - env->cp15.c2_base_mask = 0xffffc000u; + A32_BANKED_CURRENT_REG_SET(env, c2_base_mask, 0xffffc000u); raw_write(env, ri, 0); - env->cp15.c2_mask = 0; + A32_BANKED_CURRENT_REG_SET(env, c2_mask, 0); } static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4018,7 +4021,7 @@ static bool get_level1_table_address(CPUARMState *env, uint32_t *table, * Aarch32 there is a secure and non-secure instance of the translation * table registers. */ - if (address & env->cp15.c2_mask) { + if (address & A32_BANKED_CURRENT_REG_GET(env, c2_mask)) { if (A32_BANKED_CURRENT_REG_GET(env, ttbcr) & TTBCR_PD1) { /* Translation table walk disabled for TTBR1 */ return false; @@ -4030,7 +4033,7 @@ static bool get_level1_table_address(CPUARMState *env, uint32_t *table, return false; } *table = A32_BANKED_CURRENT_REG_GET(env, ttbr0) & - env->cp15.c2_base_mask; + A32_BANKED_CURRENT_REG_GET(env, c2_base_mask); } *table |= (address >> 18) & 0x3ffc; return true;