From patchwork Mon Jun 30 23:09:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 32820 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ig0-f198.google.com (mail-ig0-f198.google.com [209.85.213.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 1517A203C0 for ; Tue, 1 Jul 2014 00:01:19 +0000 (UTC) Received: by mail-ig0-f198.google.com with SMTP id h3sf20000528igd.5 for ; Mon, 30 Jun 2014 17:01:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=TO0ZnyXH5oYxpkEVnLVB/gr2O8qfd3pgmeoXavTVh00=; b=Q5g/1/REy3CEnCn68xdFziSEwmrKYd58MRlr8CJZXR+9+5Jl7DoxsTyvzsF/JVVxBX pb1N5kpdOMXyxNa0fiaOAGp4Y69S88QhjidYPnQLSZtBd/uSOSTvWubq4Nxz/kfHK0z5 lOEQgzddgl9wR2HkZzyu0FqRJpqAYUyKMQy+a+vLuXdEbPU1ZKiBNcqHQJ44NxkUzd/o 0tVTlXs6b/izut5kM2eiMFna7XBKbjVig0LqRrZRkRaiCvwPzmcYtaijuesvGABkVoKy 00vpjZ9zphzWEeEUDq3zww2zAt54TiORRUD/gK4oJ09FfxYw3SUHvZGZandGV2Fks/2H HkaA== X-Gm-Message-State: ALoCoQl6YHyXphpEjYpXcxy/lfxwtP/vGR8V0rXgtH2vFkOS05lWGHMA6/e4FzLWtzeQfpCk6zRv X-Received: by 10.182.33.106 with SMTP id q10mr23892385obi.8.1404172879352; Mon, 30 Jun 2014 17:01:19 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.82.168 with SMTP id h37ls266356qgd.62.gmail; Mon, 30 Jun 2014 17:01:19 -0700 (PDT) X-Received: by 10.220.190.197 with SMTP id dj5mr40591082vcb.19.1404172879244; Mon, 30 Jun 2014 17:01:19 -0700 (PDT) Received: from mail-ve0-f170.google.com (mail-ve0-f170.google.com [209.85.128.170]) by mx.google.com with ESMTPS id pz7si10753205vcb.5.2014.06.30.17.01.19 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 17:01:19 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.170 as permitted sender) client-ip=209.85.128.170; Received: by mail-ve0-f170.google.com with SMTP id i13so8888145veh.15 for ; Mon, 30 Jun 2014 17:01:19 -0700 (PDT) X-Received: by 10.58.12.73 with SMTP id w9mr3019972veb.13.1404172879139; Mon, 30 Jun 2014 17:01:19 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp176879vcb; Mon, 30 Jun 2014 17:01:18 -0700 (PDT) X-Received: by 10.224.29.201 with SMTP id r9mr66236382qac.25.1404172878663; Mon, 30 Jun 2014 17:01:18 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f104si16337855qgd.63.2014.06.30.17.01.18 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 30 Jun 2014 17:01:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:37129 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1ks7-0007GD-GG for patch@linaro.org; Mon, 30 Jun 2014 19:20:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53746) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kjE-0006MH-D3 for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kj8-0003b4-Mn for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:16 -0400 Received: from mail-oa0-f44.google.com ([209.85.219.44]:49799) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kj8-0003ao-Ig for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:10 -0400 Received: by mail-oa0-f44.google.com with SMTP id i7so9750021oag.31 for ; Mon, 30 Jun 2014 16:11:10 -0700 (PDT) X-Received: by 10.60.46.229 with SMTP id y5mr46636934oem.7.1404169870208; Mon, 30 Jun 2014 16:11:10 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id cu7sm76370192oec.12.2014.06.30.16.11.08 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 16:11:09 -0700 (PDT) From: greg.bellows@linaro.org To: qemu-devel@nongnu.org Date: Mon, 30 Jun 2014 18:09:22 -0500 Message-Id: <1404169773-20264-23-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.219.44 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 22/33] target-arm: make CSSELR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Rename CSSELR (cache size selection register) and add secure instance (Aarch32). Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 9 +++++---- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 1fcccc8..bc8291a 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -177,7 +177,15 @@ typedef struct CPUARMState { /* System control coprocessor (cp15) */ struct { uint32_t c0_cpuid; - uint64_t c0_cssel; /* Cache size selection. */ + union { /* Cache size selection */ + struct { + uint64_t csselr_ns; + uint64_t csselr_s; + }; + struct { + uint64_t csselr_el1; + }; + }; union { /* System control register. */ struct { uint64_t sctlr_ns; diff --git a/target-arm/helper.c b/target-arm/helper.c index 3b663f1..4a3b463 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -700,7 +700,7 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = arm_env_get_cpu(env); - return cpu->ccsidr[env->cp15.c0_cssel]; + return cpu->ccsidr[A32_BANKED_REG_GET(env, csselr)]; } static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -808,10 +808,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, - { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, + { .name = "CSSELR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel), - .writefn = csselr_write, .resetvalue = 0 }, + .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), + offsetof(CPUARMState, cp15.csselr_el1) } }, /* Auxiliary ID register: this actually has an IMPDEF value but for now * just RAZ for all cores: */