From patchwork Mon Jun 30 23:09:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 32836 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ob0-f198.google.com (mail-ob0-f198.google.com [209.85.214.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id F18F6203F4 for ; Tue, 1 Jul 2014 00:55:34 +0000 (UTC) Received: by mail-ob0-f198.google.com with SMTP id uy5sf55195742obc.9 for ; Mon, 30 Jun 2014 17:55:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=ISH22jGDID4O44xhA4lEHLbOqQhrPX9GZF+81jUAoJU=; b=LzOB/0V7fa/8E47DUrwOqsInJ1WKtGHx5u3269Uy8EMqlI3lFlf/cKBcN4TWriEY/g p3uMWkbCUZWmPhbdfZiCtJSAS/IPpYkmTJyg+8koQewJIByMqXll9SLHd1XMvfNaH37X nzhY/CBlC81EoYYwMNsXi9XqYvoGcGL8kwusgLi1v/n9hCTLLiPlsQgK8r0tCRMoz5p7 R3czE99C/Y9u33hdvTQ8aZfovwSw5Qx/Dgc5GSAOx4baY4PiAWtY1BkcdJPgpFPzKPI7 XExSld+37Ey9nMwhXjJv0CNPdBn1U+5dKXlctQGHJ6kIG5v5YqNgSoMUPQcBBSO3YBYn Uj1A== X-Gm-Message-State: ALoCoQm0w6iP3bWxZ6nqbeQ4l9Af3E0iUFhb8pFS6PoQcXkg4N9rCegXjGgJgx4vC5mcjdlVsIsn X-Received: by 10.182.213.135 with SMTP id ns7mr22356863obc.46.1404176134618; Mon, 30 Jun 2014 17:55:34 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.85.40 with SMTP id m37ls1741102qgd.18.gmail; Mon, 30 Jun 2014 17:55:34 -0700 (PDT) X-Received: by 10.221.44.73 with SMTP id uf9mr41573323vcb.9.1404176134493; Mon, 30 Jun 2014 17:55:34 -0700 (PDT) Received: from mail-vc0-f176.google.com (mail-vc0-f176.google.com [209.85.220.176]) by mx.google.com with ESMTPS id ya3si10788133vec.105.2014.06.30.17.55.34 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 17:55:34 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.176 as permitted sender) client-ip=209.85.220.176; Received: by mail-vc0-f176.google.com with SMTP id ik5so8174058vcb.7 for ; Mon, 30 Jun 2014 17:55:34 -0700 (PDT) X-Received: by 10.58.210.168 with SMTP id mv8mr38246533vec.12.1404176134390; Mon, 30 Jun 2014 17:55:34 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp179438vcb; Mon, 30 Jun 2014 17:55:34 -0700 (PDT) X-Received: by 10.224.54.133 with SMTP id q5mr67623135qag.84.1404176133987; Mon, 30 Jun 2014 17:55:33 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b109si27518149qgf.22.2014.06.30.17.55.33 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 30 Jun 2014 17:55:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:37120 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kr4-0005wd-HQ for patch@linaro.org; Mon, 30 Jun 2014 19:19:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53485) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kj4-00064x-C9 for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kiz-0003TC-HH for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:06 -0400 Received: from mail-ob0-f171.google.com ([209.85.214.171]:64432) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kiz-0003Sv-DH for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:01 -0400 Received: by mail-ob0-f171.google.com with SMTP id nu7so9637482obb.2 for ; Mon, 30 Jun 2014 16:11:01 -0700 (PDT) X-Received: by 10.182.115.232 with SMTP id jr8mr45971259obb.35.1404169861142; Mon, 30 Jun 2014 16:11:01 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id cu7sm76370192oec.12.2014.06.30.16.10.59 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 16:11:00 -0700 (PDT) From: greg.bellows@linaro.org To: qemu-devel@nongnu.org Date: Mon, 30 Jun 2014 18:09:18 -0500 Message-Id: <1404169773-20264-19-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.171 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Sergey Fedorov , Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 18/33] target-arm: add macros to access banked registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler If EL3 is in Aarch32 state certain cp registers are banked (secure and non-secure instance). When reading or writing to coprocessor registers the following macros can be used. If the CPU is in monitor mode SCR.NS bit determines which instance is going to be accessed. - USE_SECURE_REG(env): to determine which instance to use, depends on SCR.NS bit - A32_BANKED_REG_GET(env, regname): get value of banked register - A32_BANKED_REG_SET(env, regname): set value of banked register When accessing banked registers otherwise use s/ns field depending on whether CPU is in secure state (monitor mode or ns-bit clear). - A32_BANKED_CURRENT_REG_GET(env, regname) - A32_BANKED_CURRENT_REG_SET(env, regname) If EL3 is operating in Aarch64 state coprocessor registers are not banked anymore. The macros use the non-secure instance (_ns) in this case, which is architecturally mapped to the Aarch64 EL register. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index a2dab08..baf6281 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -790,6 +790,41 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return arm_feature(env, ARM_FEATURE_AARCH64); } +/* When EL3 is operating in Aarch32 state, the NS-bit determines + * whether the secure instance of a cp-register should be used. */ +#define USE_SECURE_REG(env) ( \ + arm_feature(env, ARM_FEATURE_EL3) && \ + !arm_el_is_aa64(env, 3) && \ + !((env)->cp15.scr_el3 & SCR_NS)) + +#define A32_BANKED_REG_GET(env, regname) \ + ((USE_SECURE_REG(env)) ? \ + (env)->cp15.regname##_s : \ + (env)->cp15.regname##_ns) + +#define A32_BANKED_REG_SET(env, regname, val) \ + do { \ + if (USE_SECURE_REG(env)) { \ + (env)->cp15.regname##_s = (val); \ + } else { \ + (env)->cp15.regname##_ns = (val); \ + } \ + } while (0) + +#define A32_BANKED_CURRENT_REG_GET(env, regname) \ + ((!arm_el_is_aa64(env, 3) && arm_is_secure(env)) ? \ + (env)->cp15.regname##_s : \ + (env)->cp15.regname##_ns) + +#define A32_BANKED_CURRENT_REG_SET(env, regname, val) \ + do { \ + if (!arm_el_is_aa64(env, 3) && arm_is_secure(env)) { \ + (env)->cp15.regname##_s = (val); \ + } else { \ + (env)->cp15.regname##_ns = (val); \ + } \ + } while (0) + void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx); inline uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t *target_mode,