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[99.179.1.128]) by mx.google.com with ESMTPSA id cu7sm76370192oec.12.2014.06.30.16.10.38 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 16:10:39 -0700 (PDT) From: greg.bellows@linaro.org To: qemu-devel@nongnu.org Date: Mon, 30 Jun 2014 18:09:09 -0500 Message-Id: <1404169773-20264-10-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.172 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 09/33] target-arm: extend Aarch32 async excp masking X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler This patch extends arm_excp_unmasked() according to ARM ARMv7 and ARM ARMv8 (all EL running in Aarch32) and adds comments. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 77 ++++++++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 61 insertions(+), 16 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 44e0943..fbd7cad 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -597,6 +597,8 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_IRQ (1U << 1) #define SCR_FIQ (1U << 2) #define SCR_EA (1U << 3) +#define SCR_FW (1U << 4) +#define SCR_AW (1U << 5) #define SCR_SMD (1U << 7) #define SCR_HCE (1U << 8) #define SCR_SIF (1U << 9) @@ -1199,30 +1201,73 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) { CPUARMState *env = cs->env_ptr; unsigned int cur_el = arm_current_pl(env); - unsigned int target_el = arm_excp_target_el(cs, excp_idx); - /* FIXME: Use actual secure state. */ - bool secure = false; - /* Interrupts can only be hypervised and routed to - * EL2 if we are in NS EL0/1. - */ - bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2; + bool secure = arm_is_secure(env); + bool irq_unmasked = ((IS_M(env) && env->regs[15] < 0xfffffff0) || !(env->daif & PSTATE_I)); - /* Don't take exceptions if they target a lower EL. */ - if (cur_el > target_el) { - return false; - } - + /* ARM ARMv7 B1.8.6 Asynchronous exception masking (table B1-12/B1-13) + * ARM ARMv8 G1.11.3 Asynchronous exception masking controls + * (table G1-18/G1-19) */ switch (excp_idx) { case EXCP_FIQ: - if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_FMO)) { - return true; + if (!secure) { + if (arm_feature(env, ARM_FEATURE_EL2) && + (env->cp15.hcr_el2 & HCR_FMO)) { + /* CPSR.F/PSTATE.F ignored if + * - exception is taken from Non-secure state + * - HCR.FMO == 1 + * - either: - not in Hyp mode + * - SCR.FIQ routes exception to monitor mode + */ + if (cur_el < 2) { + return true; + } else if (arm_feature(env, ARM_FEATURE_EL3) && + (env->cp15.scr_el3 & SCR_FIQ)) { + return true; + } + } + /* In ARMv7 only applies if both Security Extensions (EL3) and + * Hypervirtualization Extensions (EL2) implemented, while + * for ARMv8 it applies also if only EL3 implemented. + */ + if (arm_feature(env, ARM_FEATURE_EL3) && + (arm_feature(env, ARM_FEATURE_EL2) || + arm_feature(env, ARM_FEATURE_V8))) { + /* CPSR.F/PSTATE.F ignored if + * - exception is taken from Non-secure state + * - SCR.FIQ routes exception to monitor mode + * - SCR.FW bit is set to 0 + * - HCR.FMO == 0 (if EL2 implemented) + */ + if ((env->cp15.scr_el3 & SCR_FIQ) && + !(env->cp15.scr_el3 & SCR_FW)) { + if (!arm_feature(env, ARM_FEATURE_EL2)) { + return true; + } else if (!(env->cp15.hcr_el2 & HCR_FMO)) { + return true; + } + } + } } return !(env->daif & PSTATE_F); case EXCP_IRQ: - if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) { - return true; + if (!secure) { + if (arm_feature(env, ARM_FEATURE_EL2) && + (env->cp15.hcr_el2 & HCR_IMO)) { + /* CPSR.I/PSTATE.I ignored if + * - exception is taken from Non-secure state + * - HCR.IMO == 1 + * - either: - not in Hyp mode + * - SCR.IRQ routes exception to monitor mode + */ + if (cur_el < 2) { + return true; + } else if (arm_feature(env, ARM_FEATURE_EL3) && + (env->cp15.scr_el3 & SCR_IRQ)) { + return true; + } + } } return irq_unmasked; case EXCP_VFIQ: