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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id e62si18143116qga.51.2014.06.02.09.27.39 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 02 Jun 2014 09:27:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:47771 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WrV5H-00031S-8o for patch@linaro.org; Mon, 02 Jun 2014 12:27:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39570) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WrV0j-0005a3-Jq for qemu-devel@nongnu.org; Mon, 02 Jun 2014 12:23:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WrV0c-0007Kn-1E for qemu-devel@nongnu.org; Mon, 02 Jun 2014 12:22:57 -0400 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:41901 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WrV0b-0007Kb-Rn for qemu-devel@nongnu.org; Mon, 02 Jun 2014 12:22:49 -0400 Received: from localhost ([127.0.0.1] helo=zen.linaro.local) by socrates.bennee.com with esmtp (Exim 4.80) (envelope-from ) id 1WrV1k-0007B7-FJ; Mon, 02 Jun 2014 18:24:00 +0200 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Mon, 2 Jun 2014 17:22:02 +0100 Message-Id: <1401726122-11132-9-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1401726122-11132-1-git-send-email-alex.bennee@linaro.org> References: <1401726122-11132-1-git-send-email-alex.bennee@linaro.org> X-SA-Exim-Connect-IP: 127.0.0.1 X-SA-Exim-Mail-From: alex.bennee@linaro.org X-SA-Exim-Scanned: No (on socrates.bennee.com); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 88.198.71.155 Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, Riku Voipio , =?UTF-8?q?Alex=20Benn=C3=A9e?= , greg.bellows@linaro.org Subject: [Qemu-devel] [RCF PATCH 8/8] target-arm: remove final users of pstate_write X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: alex.bennee@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This converts all users of pstate_write to use the common state save/restore functionality. diff --git a/linux-user/signal.c b/linux-user/signal.c index c155bbc..48885e2 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -1290,7 +1290,7 @@ static int target_restore_sigframe(CPUARMState *env, __get_user(env->xregs[31], &sf->uc.tuc_mcontext.sp); __get_user(env->pc, &sf->uc.tuc_mcontext.pc); __get_user(pstate, &sf->uc.tuc_mcontext.pstate); - pstate_write(env, pstate); + restore_state_from_spsr(env, pstate); __get_user(magic, &aux->fpsimd.head.magic); __get_user(size, &aux->fpsimd.head.size); diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c4727f7..e6723dc 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -460,20 +460,6 @@ int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, #define PSTATE_MODE_EL1t 4 #define PSTATE_MODE_EL0t 0 -/* Update the current PSTATE value. This doesn't include nRW which - * indicates if we are in 64 or 32 bit mode */ -static inline void pstate_write(CPUARMState *env, uint32_t val) -{ - g_assert(is_a64(env)); - - env->ZF = (~val) & PSTATE_Z; - env->NF = val; - env->CF = (val >> 29) & 1; - env->VF = (val << 3) & 0x80000000; - env->daif = val & PSTATE_DAIF; - env->pstate = val & ~AARCH64_CACHED_PSTATE_BITS; -} - /* ARMv7-M ARM B1.4.2, special purpose program status register xPSR */ static inline uint32_t xpsr_read(CPUARMState *env) { diff --git a/target-arm/gdbstub64.c b/target-arm/gdbstub64.c index 76d1b91..366335a 100644 --- a/target-arm/gdbstub64.c +++ b/target-arm/gdbstub64.c @@ -63,7 +63,7 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 8; case 33: /* SPSR */ - pstate_write(env, tmp); + restore_state_from_spsr(env, tmp); return 4; } /* Unknown register. */ diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 1ca3164..bb48014 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -507,9 +507,8 @@ void aarch64_cpu_do_interrupt(CPUState *cs) env->condexec_bits = 0; } - // TODO: restore_state_from_spsr() - env->aarch64 = 1; - pstate_write(env, PSTATE_DAIF | PSTATE_MODE_EL1h); + /* start IRQ with a clean program state */ + restore_state_from_spsr(env, PSTATE_DAIF | PSTATE_MODE_EL1h); env->pc = addr; cs->interrupt_request |= CPU_INTERRUPT_EXITTB; diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index 83df952..8578fa9 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -222,7 +222,7 @@ int kvm_arch_get_registers(CPUState *cs) if (ret) { return ret; } - pstate_write(env, val); + restore_state_from_spsr(env, val); /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the * QEMU side we keep the current SP in xregs[31] as well.