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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id s90si18147617qga.18.2014.06.02.09.24.59 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 02 Jun 2014 09:24:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:47740 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WrV2h-0007O1-2V for patch@linaro.org; Mon, 02 Jun 2014 12:24:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39482) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WrV0U-00058S-7x for qemu-devel@nongnu.org; Mon, 02 Jun 2014 12:22:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WrV0M-0007Ho-Oh for qemu-devel@nongnu.org; Mon, 02 Jun 2014 12:22:42 -0400 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:41883 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WrV0M-0007Hk-J4 for qemu-devel@nongnu.org; Mon, 02 Jun 2014 12:22:34 -0400 Received: from localhost ([127.0.0.1] helo=zen.linaro.local) by socrates.bennee.com with esmtp (Exim 4.80) (envelope-from ) id 1WrV1V-0007B7-93; Mon, 02 Jun 2014 18:23:45 +0200 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Mon, 2 Jun 2014 17:21:57 +0100 Message-Id: <1401726122-11132-4-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1401726122-11132-1-git-send-email-alex.bennee@linaro.org> References: <1401726122-11132-1-git-send-email-alex.bennee@linaro.org> X-SA-Exim-Connect-IP: 127.0.0.1 X-SA-Exim-Mail-From: alex.bennee@linaro.org X-SA-Exim-Scanned: No (on socrates.bennee.com); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 88.198.71.155 Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , greg.bellows@linaro.org Subject: [Qemu-devel] [RCF PATCH 3/8] target-arm: Support save/load for 64 bit CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: alex.bennee@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.182 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This enables the saving and restoring of machine state by including the current program state (*psr) and xregs. The save_state_to_spsr hides the details of if the processor is in 32 or 64 bit mode at the time. --- v2 (ajb) - use common state save functions - re-base to latest origin/master - clean up commented out code diff --git a/target-arm/machine.c b/target-arm/machine.c index 3bcc7cc..759610c 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -120,30 +120,27 @@ static const VMStateDescription vmstate_thumb2ee = { } }; -static int get_cpsr(QEMUFile *f, void *opaque, size_t size) +static int get_psr(QEMUFile *f, void *opaque, size_t size) { ARMCPU *cpu = opaque; CPUARMState *env = &cpu->env; uint32_t val = qemu_get_be32(f); - /* Avoid mode switch when restoring CPSR */ - env->uncached_cpsr = val & CPSR_M; - cpsr_write(env, val, 0xffffffff); + restore_state_from_spsr(env, val); return 0; } -static void put_cpsr(QEMUFile *f, void *opaque, size_t size) +static void put_psr(QEMUFile *f, void *opaque, size_t size) { ARMCPU *cpu = opaque; CPUARMState *env = &cpu->env; - - qemu_put_be32(f, cpsr_read(env)); + qemu_put_be32(f, save_state_to_spsr(env)); } -static const VMStateInfo vmstate_cpsr = { +static const VMStateInfo vmstate_psr = { .name = "cpsr", - .get = get_cpsr, - .put = put_cpsr, + .get = get_psr, + .put = put_psr, }; static void cpu_pre_save(void *opaque) @@ -218,17 +215,19 @@ static int cpu_post_load(void *opaque, int version_id) const VMStateDescription vmstate_arm_cpu = { .name = "cpu", - .version_id = 20, - .minimum_version_id = 20, + .version_id = 21, + .minimum_version_id = 21, .pre_save = cpu_pre_save, .post_load = cpu_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), + VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), + VMSTATE_UINT64(env.pc, ARMCPU), { - .name = "cpsr", + .name = "psr", .version_id = 0, .size = sizeof(uint32_t), - .info = &vmstate_cpsr, + .info = &vmstate_psr, .flags = VMS_SINGLE, .offset = 0, },