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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id me7si4215482qcb.21.2014.05.22.04.22.27 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 22 May 2014 04:22:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:36748 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WnR4t-0007Ej-FH for patch@linaro.org; Thu, 22 May 2014 07:22:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50364) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WnR27-0002sJ-CE for qemu-devel@nongnu.org; Thu, 22 May 2014 07:19:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WnR20-0005K7-RT for qemu-devel@nongnu.org; Thu, 22 May 2014 07:19:35 -0400 Received: from mail-pa0-f54.google.com ([209.85.220.54]:47649) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WnR20-0005Ju-N4 for qemu-devel@nongnu.org; Thu, 22 May 2014 07:19:28 -0400 Received: by mail-pa0-f54.google.com with SMTP id bj1so2388806pad.41 for ; Thu, 22 May 2014 04:19:28 -0700 (PDT) X-Received: by 10.66.139.168 with SMTP id qz8mr66046658pab.3.1400757567995; Thu, 22 May 2014 04:19:27 -0700 (PDT) Received: from pnqlab006.amcc.com ([182.73.239.130]) by mx.google.com with ESMTPSA id xr9sm118782087pab.5.2014.05.22.04.19.24 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 22 May 2014 04:19:27 -0700 (PDT) From: Pranavkumar Sawargaonkar To: qemu-devel@nongnu.org Date: Thu, 22 May 2014 16:48:05 +0530 Message-Id: <1400757486-2860-8-git-send-email-pranavkumar@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1400757486-2860-1-git-send-email-pranavkumar@linaro.org> References: <1400757486-2860-1-git-send-email-pranavkumar@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.54 Cc: peter.maydell@linaro.org, Anup Patel , patches@apm.com, robherring2@gmail.com, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, Pranavkumar Sawargaonkar Subject: [Qemu-devel] [PATCH V6 7/8] target-arm: Introduce per-CPU field for PSCI version X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: pranavkumar@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 We require to know the PSCI version available to given CPU at potentially many places. Currently, we need to know PSCI version when generating DTB for virt machine. This patch introduce per-CPU 32bit field representing the PSCI version available to the CPU. The encoding of this 32bit field is same as described in PSCI v0.2 spec. Signed-off-by: Pranavkumar Sawargaonkar Signed-off-by: Anup Patel Reviewed-by: Peter Maydell --- target-arm/cpu-qom.h | 6 ++++++ target-arm/cpu.c | 1 + target-arm/kvm32.c | 1 + target-arm/kvm64.c | 1 + 4 files changed, 9 insertions(+) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 2bd7df8..eaee944 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -94,6 +94,12 @@ typedef struct ARMCPU { /* 'compatible' string for this CPU for Linux device trees */ const char *dtb_compatible; + /* PSCI version for this CPU + * Bits[31:16] = Major Version + * Bits[15:0] = Minor Version + */ + uint32_t psci_version; + /* Should CPU start in PSCI powered-off state? */ bool start_powered_off; diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 6c6f2b3..589f34d 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -260,6 +260,7 @@ static void arm_cpu_initfn(Object *obj) * picky DTB consumer will also provide a helpful error message. */ cpu->dtb_compatible = "qemu,unknown"; + cpu->psci_version = 1; /* By default assume PSCI v0.1 */ cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; if (tcg_enabled() && !inited) { diff --git a/target-arm/kvm32.c b/target-arm/kvm32.c index 52d626c..068af7d 100644 --- a/target-arm/kvm32.c +++ b/target-arm/kvm32.c @@ -184,6 +184,7 @@ int kvm_arch_init_vcpu(CPUState *cs) cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF; } if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { + cpu->psci_version = 2; cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2; } diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index feeac4a..2634baf 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -92,6 +92,7 @@ int kvm_arch_init_vcpu(CPUState *cs) cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF; } if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { + cpu->psci_version = 2; cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2; }