From patchwork Fri May 9 15:56:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 29912 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ie0-f198.google.com (mail-ie0-f198.google.com [209.85.223.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id BD37E20534 for ; Fri, 9 May 2014 15:56:09 +0000 (UTC) Received: by mail-ie0-f198.google.com with SMTP id rp18sf20562743iec.5 for ; Fri, 09 May 2014 08:56:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=18OHBRBLIgsGT6uIQH66A26x2L+Cy6L3Fg2k56KeTXg=; b=BCaIJ2tEuA1Oz6oU9ai8cjqObd2H7wNHDYSEbXvUVq0QC72ZXHfdVNARhMdbyjoU19 3e+pdU+64ayfhb220AvYB5HtGcr7rNDPKf60Yp8EvT1oeG/1rWPK8q29eGK7WElG2mYc JsapmVLL+9vb3FfQU+H6iKsKJh6n9xJts8bGimhzNrqaSacWmF9me9WHP2B+KYwE6wr1 tOFKUbhhE94c5g2yF/VK+tj7g4o7DQU2XaY4Ri7Wka7d0/3uoRO+dAcO6h1eDMmBuLFF pL+oO/mjR5IYhbp5OF7XkK1LflHj9fAIXqsUK+96IYW0Fkc2xchbMwmujdNoRn4W9qAU Bb8g== X-Gm-Message-State: ALoCoQkPyqZLh9W8GjKIify1jpRWqwKnn9BkULK2zfG2bftNXA25kUxWJj8mIsHp4kcmzDQeS81M X-Received: by 10.43.125.196 with SMTP id gt4mr4885720icc.32.1399650969262; Fri, 09 May 2014 08:56:09 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.109.71 with SMTP id k65ls388147qgf.88.gmail; Fri, 09 May 2014 08:56:09 -0700 (PDT) X-Received: by 10.58.154.10 with SMTP id vk10mr9113363veb.18.1399650969118; Fri, 09 May 2014 08:56:09 -0700 (PDT) Received: from mail-ve0-f176.google.com (mail-ve0-f176.google.com [209.85.128.176]) by mx.google.com with ESMTPS id sc7si792567vdc.31.2014.05.09.08.56.09 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 09 May 2014 08:56:09 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.176 as permitted sender) client-ip=209.85.128.176; Received: by mail-ve0-f176.google.com with SMTP id jz11so5397108veb.7 for ; Fri, 09 May 2014 08:56:09 -0700 (PDT) X-Received: by 10.220.105.130 with SMTP id t2mr9163782vco.18.1399650968994; Fri, 09 May 2014 08:56:08 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp92036vcb; Fri, 9 May 2014 08:56:08 -0700 (PDT) X-Received: by 10.152.20.40 with SMTP id k8mr901536lae.62.1399650967297; Fri, 09 May 2014 08:56:07 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id j3si2358500lbp.90.2014.05.09.08.56.06 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 09 May 2014 08:56:07 -0700 (PDT) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Win9Y-0005UO-EB; Fri, 09 May 2014 16:56:04 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Anthony Liguori , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH v2 2/4] arm_gic: Use new qom_private macro to mark private fields Date: Fri, 9 May 2014 16:56:02 +0100 Message-Id: <1399650964-21067-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1399650964-21067-1-git-send-email-peter.maydell@linaro.org> References: <1399650964-21067-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Use the new qom_private macro infrastructure to mark private fields for the arm_gic classes. Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 3 ++ hw/intc/arm_gic_common.c | 2 ++ hw/intc/arm_gic_kvm.c | 2 ++ hw/intc/armv7m_nvic.c | 2 ++ include/hw/intc/arm_gic.h | 12 ++++++-- include/hw/intc/arm_gic_common.h | 62 +++++++++++++++++++++++----------------- 6 files changed, 54 insertions(+), 29 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 1532ef9..afe2179 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -18,6 +18,9 @@ * armv7m_nvic device. */ +#define IMPLEMENTING_ARM_GIC +#define IMPLEMENTING_ARM_GIC_COMMON + #include "hw/sysbus.h" #include "gic_internal.h" #include "qom/cpu.h" diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 6d884ec..8a2c434 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -18,6 +18,8 @@ * with this program; if not, see . */ +#define IMPLEMENTING_ARM_GIC_COMMON + #include "gic_internal.h" static void gic_pre_save(void *opaque) diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 5038885..792073e 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -19,6 +19,8 @@ * with this program; if not, see . */ +#define IMPLEMENTING_ARM_GIC_COMMON + #include "hw/sysbus.h" #include "sysemu/kvm.h" #include "kvm_arm.h" diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 9aa8ab2..d68b286 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -10,6 +10,8 @@ * NVIC. Much of that is also implemented here. */ +#define IMPLEMENTING_ARM_GIC_COMMON + #include "hw/sysbus.h" #include "qemu/timer.h" #include "hw/arm/arm.h" diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index 0971e37..8d69e02 100644 --- a/include/hw/intc/arm_gic.h +++ b/include/hw/intc/arm_gic.h @@ -31,12 +31,20 @@ #define ARM_GIC_GET_CLASS(obj) \ OBJECT_GET_CLASS(ARMGICClass, (obj), TYPE_ARM_GIC) +#ifdef IMPLEMENTING_ARM_GIC +#define qom_private +#else +#define qom_private QEMU_PRIVATE_ATTR +#endif + typedef struct ARMGICClass { /*< private >*/ - ARMGICCommonClass parent_class; + qom_private ARMGICCommonClass parent_class; /*< public >*/ - DeviceRealize parent_realize; + qom_private DeviceRealize parent_realize; } ARMGICClass; +#undef qom_private + #endif diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index f6887ed..39211bd 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -44,39 +44,45 @@ typedef struct gic_irq_state { bool edge_trigger; /* true: edge-triggered, false: level-triggered */ } gic_irq_state; +#ifdef IMPLEMENTING_ARM_GIC_COMMON +#define qom_private +#else +#define qom_private QEMU_PRIVATE_ATTR +#endif + typedef struct GICState { /*< private >*/ - SysBusDevice parent_obj; + qom_private SysBusDevice parent_obj; /*< public >*/ - qemu_irq parent_irq[GIC_NCPU]; - bool enabled; - bool cpu_enabled[GIC_NCPU]; + qom_private qemu_irq parent_irq[GIC_NCPU]; + qom_private bool enabled; + qom_private bool cpu_enabled[GIC_NCPU]; - gic_irq_state irq_state[GIC_MAXIRQ]; - uint8_t irq_target[GIC_MAXIRQ]; - uint8_t priority1[GIC_INTERNAL][GIC_NCPU]; - uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL]; - uint16_t last_active[GIC_MAXIRQ][GIC_NCPU]; + qom_private gic_irq_state irq_state[GIC_MAXIRQ]; + qom_private uint8_t irq_target[GIC_MAXIRQ]; + qom_private uint8_t priority1[GIC_INTERNAL][GIC_NCPU]; + qom_private uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL]; + qom_private uint16_t last_active[GIC_MAXIRQ][GIC_NCPU]; /* For each SGI on the target CPU, we store 8 bits * indicating which source CPUs have made this SGI * pending on the target CPU. These correspond to * the bytes in the GIC_SPENDSGIR* registers as * read by the target CPU. */ - uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU]; + qom_private uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU]; - uint16_t priority_mask[GIC_NCPU]; - uint16_t running_irq[GIC_NCPU]; - uint16_t running_priority[GIC_NCPU]; - uint16_t current_pending[GIC_NCPU]; + qom_private uint16_t priority_mask[GIC_NCPU]; + qom_private uint16_t running_irq[GIC_NCPU]; + qom_private uint16_t running_priority[GIC_NCPU]; + qom_private uint16_t current_pending[GIC_NCPU]; /* We present the GICv2 without security extensions to a guest and * therefore the guest can configure the GICC_CTLR to configure group 1 * binary point in the abpr. */ - uint8_t bpr[GIC_NCPU]; - uint8_t abpr[GIC_NCPU]; + qom_private uint8_t bpr[GIC_NCPU]; + qom_private uint8_t abpr[GIC_NCPU]; /* The APR is implementation defined, so we choose a layout identical to * the KVM ABI layout for QEMU's implementation of the gic: @@ -92,19 +98,19 @@ typedef struct GICState { * do power management involving powering down and restarting * the GIC. */ - uint32_t apr[GIC_NR_APRS][GIC_NCPU]; + qom_private uint32_t apr[GIC_NR_APRS][GIC_NCPU]; - uint32_t num_cpu; + qom_private uint32_t num_cpu; - MemoryRegion iomem; /* Distributor */ + qom_private MemoryRegion iomem; /* Distributor */ /* This is just so we can have an opaque pointer which identifies * both this GIC and which CPU interface we should be accessing. */ - struct GICState *backref[GIC_NCPU]; - MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ - uint32_t num_irq; - uint32_t revision; - int dev_fd; /* kvm device fd if backed by kvm vgic support */ + qom_private struct GICState *backref[GIC_NCPU]; + qom_private MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ + qom_private uint32_t num_irq; + qom_private uint32_t revision; + qom_private int dev_fd; /* kvm device fd if backed by kvm vgic support */ } GICState; #define TYPE_ARM_GIC_COMMON "arm_gic_common" @@ -117,11 +123,13 @@ typedef struct GICState { typedef struct ARMGICCommonClass { /*< private >*/ - SysBusDeviceClass parent_class; + qom_private SysBusDeviceClass parent_class; /*< public >*/ - void (*pre_save)(GICState *s); - void (*post_load)(GICState *s); + qom_private void (*pre_save)(GICState *s); + qom_private void (*post_load)(GICState *s); } ARMGICCommonClass; +#undef qom_private + #endif