From patchwork Thu Apr 17 10:33:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 28575 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ie0-f200.google.com (mail-ie0-f200.google.com [209.85.223.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 1C92820674 for ; Thu, 17 Apr 2014 12:30:43 +0000 (UTC) Received: by mail-ie0-f200.google.com with SMTP id lx4sf1833780iec.7 for ; Thu, 17 Apr 2014 05:30:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=xpPnBfev28zjPAzGb9QV6ZkNeEp6Pygx7iAVgGFia5g=; b=WSi5FDXUVlQDuGvBUZDvkNdUwPYcqcWiiV71yCrk7l+PyYZpFvVA8blK0EIhSkOETG jEpBQJdFA89FwaPeEG8rJnN8Uxh8wYHrRP4+qDnym/DTYoZqyJpNhYMONbF46r1bpuue zylza9PaS4GQs0u0exB3GaEp/Ux7YbsJtp6YPcqsBSq+0P9SoqQbJW2bDtgovhzUqT23 +w1DD3nr2e9iLp0Ip10lzStKddMy0YAF2B/hwaLlQ/QOc9vALaTe7ODESOMrzScZnvur PEgXS8+vw5E4pXifrKZzb9l2F6til9SQU76/BVY3Twc53Udovljn/1CHEBq2h20bkgdd 3k0g== X-Gm-Message-State: ALoCoQn7u21CISJ5hJwPLQuM4BcNm6oIOKaiFSEigHpYIqto02453B84VGdT2mJ0E/cjcaSLWA4c X-Received: by 10.43.139.66 with SMTP id iv2mr5053148icc.17.1397737843518; Thu, 17 Apr 2014 05:30:43 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.98.229 with SMTP id o92ls1019489qge.95.gmail; Thu, 17 Apr 2014 05:30:43 -0700 (PDT) X-Received: by 10.52.65.165 with SMTP id y5mr21471vds.51.1397737843365; Thu, 17 Apr 2014 05:30:43 -0700 (PDT) Received: from mail-ve0-f176.google.com (mail-ve0-f176.google.com [209.85.128.176]) by mx.google.com with ESMTPS id sn5si4407186vdc.209.2014.04.17.05.30.43 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 17 Apr 2014 05:30:43 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.176; Received: by mail-ve0-f176.google.com with SMTP id db11so393062veb.7 for ; Thu, 17 Apr 2014 05:30:43 -0700 (PDT) X-Received: by 10.52.78.231 with SMTP id e7mr6261747vdx.28.1397737843287; Thu, 17 Apr 2014 05:30:43 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp31357vcb; Thu, 17 Apr 2014 05:30:43 -0700 (PDT) X-Received: by 10.229.17.69 with SMTP id r5mr11129439qca.7.1397737842736; Thu, 17 Apr 2014 05:30:42 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id a1si936506qar.189.2014.04.17.05.30.42 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 17 Apr 2014 05:30:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:59454 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wajk1-0005JW-M9 for patch@linaro.org; Thu, 17 Apr 2014 06:40:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50981) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WajeD-0007pq-VF for qemu-devel@nongnu.org; Thu, 17 Apr 2014 06:34:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WajeC-0002VS-RT for qemu-devel@nongnu.org; Thu, 17 Apr 2014 06:34:25 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:47842) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WajeC-0002OB-La for qemu-devel@nongnu.org; Thu, 17 Apr 2014 06:34:24 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Wajdw-00020a-Df for qemu-devel@nongnu.org; Thu, 17 Apr 2014 11:34:08 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 17 Apr 2014 11:33:39 +0100 Message-Id: <1397730846-7576-25-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1397730846-7576-1-git-send-email-peter.maydell@linaro.org> References: <1397730846-7576-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 24/51] target-arm: Implement AArch64 view of ACTLR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Implement the AArch64 view of the ACTLR (auxiliary control register). Note that QEMU internally tends to call this AUXCR for historical reasons. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- target-arm/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 10300aa..32af1df 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2316,7 +2316,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_AUXCR)) { ARMCPRegInfo auxcr = { - .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, + .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr };