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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id uk8si2070196bkb.37.2014.04.10.09.15.54 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 10 Apr 2014 09:15:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WYHda-0007sb-E6; Thu, 10 Apr 2014 17:15:38 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Peter Crosthwaite , Greg Bellows Subject: [PATCH v6 37/37] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32 Date: Thu, 10 Apr 2014 17:15:36 +0100 Message-Id: <1397146536-30116-38-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1397146536-30116-1-git-send-email-peter.maydell@linaro.org> References: <1397146536-30116-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.178 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , For system mode, we may have a 64 bit CPU which is currently executing in AArch32 state; if we're dumping CPU state to the logs we should therefore show the correct state for the current execution state, rather than hardwiring it based on the type of the CPU. For consistency with how we handle translation, we leave the 32 bit dump function as the default, and have it hand off control to the 64 bit dump code if we're in AArch64 mode. Reported-by: Rob Herring Signed-off-by: Peter Maydell --- target-arm/cpu-qom.h | 2 -- target-arm/cpu64.c | 1 - target-arm/translate.c | 5 +++++ target-arm/translate.h | 8 ++++++++ 4 files changed, 13 insertions(+), 3 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 82f1bc7..edc7f26 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -200,8 +200,6 @@ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); #ifdef TARGET_AARCH64 -void aarch64_cpu_dump_state(CPUState *cs, FILE *f, - fprintf_function cpu_fprintf, int flags); int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index c673ac2..8daa622 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -188,7 +188,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) CPUClass *cc = CPU_CLASS(oc); cc->do_interrupt = aarch64_cpu_do_interrupt; - cc->dump_state = aarch64_cpu_dump_state; cc->set_pc = aarch64_cpu_set_pc; cc->gdb_read_register = aarch64_cpu_gdb_read_register; cc->gdb_write_register = aarch64_cpu_gdb_write_register; diff --git a/target-arm/translate.c b/target-arm/translate.c index f7b5daf..0c08cc1 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11047,6 +11047,11 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int i; uint32_t psr; + if (is_a64(env)) { + aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags); + return; + } + for(i=0;i<16;i++) { cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]); if ((i % 4) == 3) diff --git a/target-arm/translate.h b/target-arm/translate.h index 3f7d5ca..34328f4 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -72,6 +72,8 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, TranslationBlock *tb, bool search_pc); void gen_a64_set_pc_im(uint64_t val); +void aarch64_cpu_dump_state(CPUState *cs, FILE *f, + fprintf_function cpu_fprintf, int flags); #else static inline void a64_translate_init(void) { @@ -86,6 +88,12 @@ static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu, static inline void gen_a64_set_pc_im(uint64_t val) { } + +static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, + fprintf_function cpu_fprintf, + int flags) +{ +} #endif void arm_gen_test_cc(int cc, int label);