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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id m6si7428727qay.264.2014.04.01.04.58.57 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 01 Apr 2014 04:58:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:59776 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WUxLE-0006eR-UJ for patch@linaro.org; Tue, 01 Apr 2014 07:58:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37101) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WUxH6-0007AE-GK for qemu-devel@nongnu.org; Tue, 01 Apr 2014 07:54:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WUxH0-0007aD-AA for qemu-devel@nongnu.org; Tue, 01 Apr 2014 07:54:40 -0400 Received: from mail-pd0-f179.google.com ([209.85.192.179]:43048) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WUxH0-0007Zw-22 for qemu-devel@nongnu.org; Tue, 01 Apr 2014 07:54:34 -0400 Received: by mail-pd0-f179.google.com with SMTP id w10so9374743pde.24 for ; Tue, 01 Apr 2014 04:54:33 -0700 (PDT) X-Received: by 10.68.202.194 with SMTP id kk2mr1790793pbc.156.1396353273251; Tue, 01 Apr 2014 04:54:33 -0700 (PDT) Received: from pnqlab006.amcc.com ([182.73.239.130]) by mx.google.com with ESMTPSA id ix2sm49532958pbc.45.2014.04.01.04.54.29 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 01 Apr 2014 04:54:32 -0700 (PDT) From: Pranavkumar Sawargaonkar To: qemu-devel@nongnu.org Date: Tue, 1 Apr 2014 17:23:51 +0530 Message-Id: <1396353232-3835-6-git-send-email-pranavkumar@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1396353232-3835-1-git-send-email-pranavkumar@linaro.org> References: <1396353232-3835-1-git-send-email-pranavkumar@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.179 Cc: peter.maydell@linaro.org, Anup Patel , patches@apm.com, kvmarm@list.cs.columbia.edu, christoffer.dall@linaro.org, Pranavkumar Sawargaonkar Subject: [Qemu-devel] [RFC PATCH V2 5/6] target-arm: Provide PSCI v0.2 constants to generic QEMU code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: pranavkumar@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Provide QEMU PSCI v0.2 constants for non-KVM code; this will allow us to avoid an #ifdef in boards which set up a PSCI v0.2 node in the device tree. Signed-off-by: Pranavkumar Sawargaonkar Signed-off-by: Anup Patel --- target-arm/kvm-consts.h | 63 ++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 52 insertions(+), 11 deletions(-) diff --git a/target-arm/kvm-consts.h b/target-arm/kvm-consts.h index 6009a33..5cf93ab 100644 --- a/target-arm/kvm-consts.h +++ b/target-arm/kvm-consts.h @@ -38,17 +38,58 @@ MISMATCH_CHECK(CP_REG_SIZE_U64, KVM_REG_SIZE_U64) MISMATCH_CHECK(CP_REG_ARM, KVM_REG_ARM) MISMATCH_CHECK(CP_REG_ARCH_MASK, KVM_REG_ARCH_MASK) -#define PSCI_FN_BASE 0x95c1ba5e -#define PSCI_FN(n) (PSCI_FN_BASE + (n)) -#define PSCI_FN_CPU_SUSPEND PSCI_FN(0) -#define PSCI_FN_CPU_OFF PSCI_FN(1) -#define PSCI_FN_CPU_ON PSCI_FN(2) -#define PSCI_FN_MIGRATE PSCI_FN(3) - -MISMATCH_CHECK(PSCI_FN_CPU_SUSPEND, KVM_PSCI_FN_CPU_SUSPEND) -MISMATCH_CHECK(PSCI_FN_CPU_OFF, KVM_PSCI_FN_CPU_OFF) -MISMATCH_CHECK(PSCI_FN_CPU_ON, KVM_PSCI_FN_CPU_ON) -MISMATCH_CHECK(PSCI_FN_MIGRATE, KVM_PSCI_FN_MIGRATE) +/* PSCI v0.1 interface */ +#define QEMU_PSCI_FN_BASE 0x95c1ba5e +#define QEMU_PSCI_FN(n) (QEMU_PSCI_FN_BASE + (n)) +#define QEMU_PSCI_FN_CPU_SUSPEND QEMU_PSCI_FN(0) +#define QEMU_PSCI_FN_CPU_OFF QEMU_PSCI_FN(1) +#define QEMU_PSCI_FN_CPU_ON QEMU_PSCI_FN(2) +#define QEMU_PSCI_FN_MIGRATE QEMU_PSCI_FN(3) + +MISMATCH_CHECK(QEMU_PSCI_FN_CPU_SUSPEND, KVM_PSCI_FN_CPU_SUSPEND) +MISMATCH_CHECK(QEMU_PSCI_FN_CPU_OFF, KVM_PSCI_FN_CPU_OFF) +MISMATCH_CHECK(QEMU_PSCI_FN_CPU_ON, KVM_PSCI_FN_CPU_ON) +MISMATCH_CHECK(QEMU_PSCI_FN_MIGRATE, KVM_PSCI_FN_MIGRATE) + +/* PSCI v0.2 interface */ +#define QEMU_PSCI_0_2_FN_BASE 0x84000000 +#define QEMU_PSCI_0_2_FN(n) (QEMU_PSCI_0_2_FN_BASE + (n)) +#define QEMU_PSCI_0_2_FN64_BASE 0xC4000000 +#define QEMU_PSCI_0_2_FN64(n) (QEMU_PSCI_0_2_FN64_BASE + (n)) +#define QEMU_PSCI_0_2_FN_PSCI_VERSION QEMU_PSCI_0_2_FN(0) +#define QEMU_PSCI_0_2_FN_CPU_SUSPEND QEMU_PSCI_0_2_FN(1) +#define QEMU_PSCI_0_2_FN_CPU_OFF QEMU_PSCI_0_2_FN(2) +#define QEMU_PSCI_0_2_FN_CPU_ON QEMU_PSCI_0_2_FN(3) +#define QEMU_PSCI_0_2_FN_AFFINITY_INFO QEMU_PSCI_0_2_FN(4) +#define QEMU_PSCI_0_2_FN_MIGRATE QEMU_PSCI_0_2_FN(5) +#define QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE QEMU_PSCI_0_2_FN(6) +#define QEMU_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU QEMU_PSCI_0_2_FN(7) +#define QEMU_PSCI_0_2_FN_SYSTEM_OFF QEMU_PSCI_0_2_FN(8) +#define QEMU_PSCI_0_2_FN_SYSTEM_RESET QEMU_PSCI_0_2_FN(9) +#define QEMU_PSCI_0_2_FN64_CPU_SUSPEND QEMU_PSCI_0_2_FN64(1) +#define QEMU_PSCI_0_2_FN64_CPU_ON QEMU_PSCI_0_2_FN64(3) +#define QEMU_PSCI_0_2_FN64_AFFINITY_INFO QEMU_PSCI_0_2_FN64(4) +#define QEMU_PSCI_0_2_FN64_MIGRATE QEMU_PSCI_0_2_FN64(5) +#define QEMU_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU QEMU_PSCI_0_2_FN64(7) + +MISMATCH_CHECK(QEMU_PSCI_0_2_FN_PSCI_VERSION, PSCI_0_2_FN_PSCI_VERSION) +MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_SUSPEND, PSCI_0_2_FN_CPU_SUSPEND) +MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_OFF, PSCI_0_2_FN_CPU_OFF) +MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_ON, PSCI_0_2_FN_CPU_ON) +MISMATCH_CHECK(QEMU_PSCI_0_2_FN_AFFINITY_INFO, PSCI_0_2_FN_AFFINITY_INFO) +MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE, PSCI_0_2_FN_MIGRATE) +MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE, \ + PSCI_0_2_FN_MIGRATE_INFO_TYPE) +MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU, \ + PSCI_0_2_FN_MIGRATE_INFO_UP_CPU) +MISMATCH_CHECK(QEMU_PSCI_0_2_FN_SYSTEM_OFF, PSCI_0_2_FN_SYSTEM_OFF) +MISMATCH_CHECK(QEMU_PSCI_0_2_FN_SYSTEM_RESET, PSCI_0_2_FN_SYSTEM_RESET) +MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_SUSPEND, PSCI_0_2_FN64_CPU_SUSPEND) +MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_ON, PSCI_0_2_FN64_CPU_ON) +MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_AFFINITY_INFO, PSCI_0_2_FN64_AFFINITY_INFO) +MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_MIGRATE, PSCI_0_2_FN64_MIGRATE) +MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU, \ + PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU) /* Note that KVM uses overlapping values for AArch32 and AArch64 * target CPU numbers. AArch32 targets: