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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id p10si9489273wie.71.2014.03.24.09.14.17 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 24 Mar 2014 09:14:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WS7Vk-0007h7-QC; Mon, 24 Mar 2014 16:14:04 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Michael Matz , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Peter Crosthwaite Subject: [PATCH for-2.0] target-arm: Fix A64 Neon MLS Date: Mon, 24 Mar 2014 16:14:04 +0000 Message-Id: <1395677644-29552-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The order of operands for the accumulate step in disas_simd_3same_int() was reversed. This only affected the MLS instruction, since all the other accumulating instructions in this category perform an addition rather than a subtraction. Reported-by: Laurent Desnogues Signed-off-by: Peter Maydell Tested-by: Laurent Desnogues --- Bit embarrassing, not sure how this slipped through the testing process (the test risu binary I have for MLS failed as expected, so I must just have forgotten to run/rerun it somehow.) target-arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 9f06450..9175e48 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -8925,7 +8925,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) genfn = fns[size][is_sub]; read_vec_element_i32(s, tcg_op1, rd, pass, MO_32); - genfn(tcg_res, tcg_res, tcg_op1); + genfn(tcg_res, tcg_op1, tcg_res); } write_vec_element_i32(s, tcg_res, rd, pass, MO_32);