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[72.48.77.163]) by mx.google.com with ESMTPSA id wj7sm33595445obc.8.2014.03.18.11.18.51 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 18 Mar 2014 11:18:52 -0700 (PDT) From: Rob Herring To: qemu-devel@nongnu.org, Peter Maydell Date: Tue, 18 Mar 2014 13:18:39 -0500 Message-Id: <1395166721-15716-2-git-send-email-robherring2@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1395166721-15716-1-git-send-email-robherring2@gmail.com> References: <1395166721-15716-1-git-send-email-robherring2@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4003:c02::22a Cc: Rob Herring Subject: [Qemu-devel] [PATCH v3 1/3] pl011: reset the fifo when enabled or disabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Original-Sender: robherring2@gmail.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c03::22b is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=fail header.i=@gmail.com; dmarc=fail (p=NONE dis=NONE) header.from=gmail.com Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Rob Herring Intermittent issues have been seen where no serial input occurs. It appears the pl011 gets in a state where the rx interrupt never fires because the rx interrupt only asserts when crossing the fifo trigger level. The fifo state appears to get out of sync when the pl011 is re-configured. This combined with the rx timeout interrupt not being modeled results in no more rx interrupts. Disabling the fifo is the recommended way to clear the tx fifo in the TRM (section 3.3.8). The behavior in this case for the rx fifo is undefined in the TRM, but having fifo contents to be maintained during configuration changes is not likely expected behavior. Reseting the fifo state when the fifo size is changed is the simplest solution. Signed-off-by: Rob Herring --- hw/char/pl011.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index a8ae6f4..8103e2e 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -162,6 +162,11 @@ static void pl011_write(void *opaque, hwaddr offset, s->fbrd = value; break; case 11: /* UARTLCR_H */ + /* Reset the FIFO state on FIFO enable or disable */ + if ((s->lcr ^ value) & 0x10) { + s->read_count = 0; + s->read_pos = 0; + } s->lcr = value; pl011_set_read_trigger(s); break;