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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 61si9603400qgw.11.2014.03.17.16.17.09 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 17 Mar 2014 16:17:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:60649 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPfuX-0005YZ-Sr for patch@linaro.org; Mon, 17 Mar 2014 18:21:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPfmJ-0004Vy-15 for qemu-devel@nongnu.org; Mon, 17 Mar 2014 18:13:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPfmI-0007SV-36 for qemu-devel@nongnu.org; Mon, 17 Mar 2014 18:13:02 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:46921) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPfmH-0007Pr-TR for qemu-devel@nongnu.org; Mon, 17 Mar 2014 18:13:02 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WPfle-00053k-1o; Mon, 17 Mar 2014 22:12:22 +0000 From: Peter Maydell To: Anthony Liguori Date: Mon, 17 Mar 2014 22:12:12 +0000 Message-Id: <1395094341-19339-22-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1395094341-19339-1-git-send-email-peter.maydell@linaro.org> References: <1395094341-19339-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: Blue Swirl , =?UTF-8?q?Andreas=20F=C3=A4rber?= , qemu-devel@nongnu.org, Aurelien Jarno Subject: [Qemu-devel] [PULL 21/30] exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.178 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The ARM A64 decoder's worst case number of TCG ops per instruction is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures store). Raise the MAX_OP_PER_INSTR define accordingly. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1394822294-14837-17-git-send-email-peter.maydell@linaro.org --- include/exec/exec-all.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 502b7aa..f9ac332 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -44,7 +44,7 @@ struct TranslationBlock; typedef struct TranslationBlock TranslationBlock; /* XXX: make safe guess about sizes */ -#define MAX_OP_PER_INSTR 208 +#define MAX_OP_PER_INSTR 266 #if HOST_LONG_BITS == 32 #define MAX_OPC_PARAM_PER_ARG 2