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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id n7si17319939eeu.199.2014.03.17.09.00.41 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 17 Mar 2014 09:00:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WPZxx-0004vv-C0; Mon, 17 Mar 2014 16:00:41 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, qemu-trivial@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v2 07/12] hw/intc/openpic: Avoid shifting left into sign bit Date: Mon, 17 Mar 2014 16:00:36 +0000 Message-Id: <1395072041-18911-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1395072041-18911-1-git-send-email-peter.maydell@linaro.org> References: <1395072041-18911-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add U suffix to avoid undefined behaviour. This is only strictly necessary for the 1 << 31 cases; for consistency we extend it to other constants in the same group. Signed-off-by: Peter Maydell --- hw/intc/openpic.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 7df72f4..be76fbd 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -123,7 +123,7 @@ static FslMpicInfo fsl_mpic_42 = { #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */ #define IDR_EP_SHIFT 31 -#define IDR_EP_MASK (1 << IDR_EP_SHIFT) +#define IDR_EP_MASK (1U << IDR_EP_SHIFT) #define IDR_CI0_SHIFT 30 #define IDR_CI1_SHIFT 29 #define IDR_P1_SHIFT 1 @@ -220,17 +220,17 @@ typedef struct IRQSource { } IRQSource; #define IVPR_MASK_SHIFT 31 -#define IVPR_MASK_MASK (1 << IVPR_MASK_SHIFT) +#define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT) #define IVPR_ACTIVITY_SHIFT 30 -#define IVPR_ACTIVITY_MASK (1 << IVPR_ACTIVITY_SHIFT) +#define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT) #define IVPR_MODE_SHIFT 29 -#define IVPR_MODE_MASK (1 << IVPR_MODE_SHIFT) +#define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT) #define IVPR_POLARITY_SHIFT 23 -#define IVPR_POLARITY_MASK (1 << IVPR_POLARITY_SHIFT) +#define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT) #define IVPR_SENSE_SHIFT 22 -#define IVPR_SENSE_MASK (1 << IVPR_SENSE_SHIFT) +#define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT) -#define IVPR_PRIORITY_MASK (0xF << 16) +#define IVPR_PRIORITY_MASK (0xFU << 16) #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16)) #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)