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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id qq5si8177683bkb.287.2014.03.10.12.10.49 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 10 Mar 2014 12:10:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WN5b7-0002TR-BN; Mon, 10 Mar 2014 19:10:49 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, qemu-trivial@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 08/12] hw/ppc: Avoid shifting left into sign bit Date: Mon, 10 Mar 2014 19:10:44 +0000 Message-Id: <1394478649-9453-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1394478649-9453-1-git-send-email-peter.maydell@linaro.org> References: <1394478649-9453-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.179 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add U suffix to various places where we were doing "1 << 31", which is undefined behaviour. Signed-off-by: Peter Maydell --- hw/ppc/ppc.c | 2 +- hw/ppc/ppc440_bamboo.c | 4 ++-- hw/ppc/ppc4xx_devs.c | 2 +- hw/ppc/ppc_booke.c | 4 ++-- hw/ppc/virtex_ml507.c | 4 ++-- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 0e82719..9c2a132 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -1002,7 +1002,7 @@ static void cpu_4xx_wdt_cb (void *opaque) case 0x1: timer_mod(ppc40x_timer->wdt_timer, next); ppc40x_timer->wdt_next = next; - env->spr[SPR_40x_TSR] |= 1 << 31; + env->spr[SPR_40x_TSR] |= 1U << 31; break; case 0x2: timer_mod(ppc40x_timer->wdt_timer, next); diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index ec15bab..2ddc2ed 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -128,7 +128,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, tlb->attr = 0; tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); - tlb->size = 1 << 31; /* up to 0x80000000 */ + tlb->size = 1U << 31; /* up to 0x80000000 */ tlb->EPN = va & TARGET_PAGE_MASK; tlb->RPN = pa & TARGET_PAGE_MASK; tlb->PID = 0; @@ -136,7 +136,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, tlb = &env->tlb.tlbe[1]; tlb->attr = 0; tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); - tlb->size = 1 << 31; /* up to 0xffffffff */ + tlb->size = 1U << 31; /* up to 0xffffffff */ tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; tlb->PID = 0; diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 9160ee7..8a43111 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -161,7 +161,7 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level) uint32_t mask, sr; uic = opaque; - mask = 1 << (31-irq_num); + mask = 1U << (31-irq_num); LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", __func__, irq_num, level, diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c index d839960..773c4ea 100644 --- a/hw/ppc/ppc_booke.c +++ b/hw/ppc/ppc_booke.c @@ -34,7 +34,7 @@ /* Timer Control Register */ #define TCR_WP_SHIFT 30 /* Watchdog Timer Period */ -#define TCR_WP_MASK (0x3 << TCR_WP_SHIFT) +#define TCR_WP_MASK (0x3U << TCR_WP_SHIFT) #define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */ #define TCR_WRC_MASK (0x3 << TCR_WRC_SHIFT) #define TCR_WIE (1 << 27) /* Watchdog Timer Interrupt Enable */ @@ -58,7 +58,7 @@ #define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */ #define TSR_WRS_MASK (0x3 << TSR_WRS_SHIFT) #define TSR_WIS (1 << 30) /* Watchdog Timer Interrupt Status */ -#define TSR_ENW (1 << 31) /* Enable Next Watchdog Timer */ +#define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */ typedef struct booke_timer_t booke_timer_t; struct booke_timer_t { diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index ce8ea91..3e3569d 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -71,7 +71,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, tlb->attr = 0; tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); - tlb->size = 1 << 31; /* up to 0x80000000 */ + tlb->size = 1U << 31; /* up to 0x80000000 */ tlb->EPN = va & TARGET_PAGE_MASK; tlb->RPN = pa & TARGET_PAGE_MASK; tlb->PID = 0; @@ -79,7 +79,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, tlb = &env->tlb.tlbe[1]; tlb->attr = 0; tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); - tlb->size = 1 << 31; /* up to 0xffffffff */ + tlb->size = 1U << 31; /* up to 0xffffffff */ tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; tlb->PID = 0;