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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id js7si19048490wjc.48.2014.03.10.12.26.50 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 10 Mar 2014 12:26:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WN5b7-0002TV-D2; Mon, 10 Mar 2014 19:10:49 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, qemu-trivial@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 09/12] tests/libqos/pci-pc: Avoid shifting left into sign bit Date: Mon, 10 Mar 2014 19:10:45 +0000 Message-Id: <1394478649-9453-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1394478649-9453-1-git-send-email-peter.maydell@linaro.org> References: <1394478649-9453-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add U suffix when doing "1 << 31" to avoid undefined behaviour. Signed-off-by: Peter Maydell --- tests/libqos/pci-pc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/libqos/pci-pc.c b/tests/libqos/pci-pc.c index 3bde8ab..bf741a4 100644 --- a/tests/libqos/pci-pc.c +++ b/tests/libqos/pci-pc.c @@ -110,37 +110,37 @@ static void qpci_pc_io_writel(QPCIBus *bus, void *addr, uint32_t value) static uint8_t qpci_pc_config_readb(QPCIBus *bus, int devfn, uint8_t offset) { - outl(0xcf8, (1 << 31) | (devfn << 8) | offset); + outl(0xcf8, (1U << 31) | (devfn << 8) | offset); return inb(0xcfc); } static uint16_t qpci_pc_config_readw(QPCIBus *bus, int devfn, uint8_t offset) { - outl(0xcf8, (1 << 31) | (devfn << 8) | offset); + outl(0xcf8, (1U << 31) | (devfn << 8) | offset); return inw(0xcfc); } static uint32_t qpci_pc_config_readl(QPCIBus *bus, int devfn, uint8_t offset) { - outl(0xcf8, (1 << 31) | (devfn << 8) | offset); + outl(0xcf8, (1U << 31) | (devfn << 8) | offset); return inl(0xcfc); } static void qpci_pc_config_writeb(QPCIBus *bus, int devfn, uint8_t offset, uint8_t value) { - outl(0xcf8, (1 << 31) | (devfn << 8) | offset); + outl(0xcf8, (1U << 31) | (devfn << 8) | offset); outb(0xcfc, value); } static void qpci_pc_config_writew(QPCIBus *bus, int devfn, uint8_t offset, uint16_t value) { - outl(0xcf8, (1 << 31) | (devfn << 8) | offset); + outl(0xcf8, (1U << 31) | (devfn << 8) | offset); outw(0xcfc, value); } static void qpci_pc_config_writel(QPCIBus *bus, int devfn, uint8_t offset, uint32_t value) { - outl(0xcf8, (1 << 31) | (devfn << 8) | offset); + outl(0xcf8, (1U << 31) | (devfn << 8) | offset); outl(0xcfc, value); }