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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id b7si4863813qad.174.2014.03.07.05.41.19 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 07 Mar 2014 05:41:19 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:36654 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WLv1b-0005qj-8j for patch@linaro.org; Fri, 07 Mar 2014 08:41:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52588) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WLuuK-00045L-4G for qemu-devel@nongnu.org; Fri, 07 Mar 2014 08:33:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WLuuF-00027c-37 for qemu-devel@nongnu.org; Fri, 07 Mar 2014 08:33:48 -0500 Received: from mx1.redhat.com ([209.132.183.28]:27296) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WLuuE-000262-QY for qemu-devel@nongnu.org; Fri, 07 Mar 2014 08:33:43 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s27DXejK006951 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Fri, 7 Mar 2014 08:33:41 -0500 Received: from dhcp-200-207.str.redhat.com (ovpn-116-75.ams2.redhat.com [10.36.116.75]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id s27DXDSa009961; Fri, 7 Mar 2014 08:33:39 -0500 From: Kevin Wolf To: qemu-devel@nongnu.org Date: Fri, 7 Mar 2014 14:33:06 +0100 Message-Id: <1394199187-9576-19-git-send-email-kwolf@redhat.com> In-Reply-To: <1394199187-9576-1-git-send-email-kwolf@redhat.com> References: <1394199187-9576-1-git-send-email-kwolf@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: kwolf@redhat.com Subject: [Qemu-devel] [PULL 18/19] hw/ide/ahci.h: Avoid shifting left into sign bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: kwolf@redhat.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Peter Maydell Add 'U' suffixes to avoid undefined behaviour shifting left into the signed bit of a signed integer type. Clang's sanitizer will warn about this: hw/ide/ahci.c:1210:27: runtime error: left shift of 1 by 31 places cannot be represented in type 'int' Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite Signed-off-by: Kevin Wolf --- hw/ide/ahci.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h index 20e412c..9a4064f 100644 --- a/hw/ide/ahci.h +++ b/hw/ide/ahci.h @@ -40,7 +40,7 @@ #define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \ AHCI_RX_FIS_SZ) -#define AHCI_IRQ_ON_SG (1 << 31) +#define AHCI_IRQ_ON_SG (1U << 31) #define AHCI_CMD_ATAPI (1 << 5) #define AHCI_CMD_WRITE (1 << 6) #define AHCI_CMD_PREFETCH (1 << 7) @@ -61,7 +61,7 @@ /* HOST_CTL bits */ #define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */ #define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */ -#define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ +#define HOST_CTL_AHCI_EN (1U << 31) /* AHCI enabled */ /* HOST_CAP bits */ #define HOST_CAP_SSC (1 << 14) /* Slumber capable */ @@ -69,7 +69,7 @@ #define HOST_CAP_CLO (1 << 24) /* Command List Override support */ #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */ #define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */ -#define HOST_CAP_64 (1 << 31) /* PCI DAC (64-bit DMA) support */ +#define HOST_CAP_64 (1U << 31) /* PCI DAC (64-bit DMA) support */ /* registers for each SATA port */ #define PORT_LST_ADDR 0x00 /* command list DMA addr */ @@ -89,7 +89,7 @@ #define PORT_RESERVED 0x3c /* reserved */ /* PORT_IRQ_{STAT,MASK} bits */ -#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ +#define PORT_IRQ_COLD_PRES (1U << 31) /* cold presence detect */ #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ @@ -151,7 +151,7 @@ #define PORT_IRQ_STAT_HBDS (1 << 28) /* Host Bus Data Error Status */ #define PORT_IRQ_STAT_HBFS (1 << 29) /* Host Bus Fatal Error Status */ #define PORT_IRQ_STAT_TFES (1 << 30) /* Task File Error Status */ -#define PORT_IRQ_STAT_CPDS (1 << 31) /* Code Port Detect Status */ +#define PORT_IRQ_STAT_CPDS (1U << 31) /* Code Port Detect Status */ /* ap->flags bits */ #define AHCI_FLAG_NO_NCQ (1 << 24)