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[72.48.77.163]) by mx.google.com with ESMTPSA id bx1sm244782oec.8.2014.02.27.16.57.53 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 27 Feb 2014 16:57:53 -0800 (PST) From: Rob Herring To: qemu-devel@nongnu.org Date: Thu, 27 Feb 2014 18:57:32 -0600 Message-Id: <1393549052-26168-1-git-send-email-robherring2@gmail.com> X-Mailer: git-send-email 1.8.3.2 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4003:c01::22a Cc: Peter Maydell , Christoffer Dall , Rob Herring Subject: [Qemu-devel] [PATCH] pl011: reset the fifo when enabled or disabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Original-Sender: robherring2@gmail.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c03::231 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=fail header.i=@gmail.com; dmarc=fail (p=NONE dis=NONE) header.from=gmail.com Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Rob Herring Intermittent issues have been seen where no serial input occurs. It appears the pl011 gets in a state where the rx interrupt never fires because the rx interrupt only asserts when crossing the fifo trigger level. The fifo state appears to get out of sync when the pl011 is re-configured. This combined with the rx timeout interrupt not being modeled results in no more rx interrupts. Disabling the fifo is the recommended way to clear the fifo in the TRM, but none of the fifo state was getting reset when the fifo was disabled. Ensure all the fifo state is reset when the fifo is enabled or disabled. When setting the fifo trigger level, the rx interrupt needs to be asserted if the current fifo level matches. Also, fix incorrect logic to set the RXFF flag. Signed-off-by: Rob Herring --- hw/char/pl011.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 8ced7cd..9260a3d 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -129,6 +129,9 @@ static void pl011_set_read_trigger(PL011State *s) else #endif s->read_trigger = 1; + + if (s->read_count == s->read_trigger) + s->int_level |= PL011_INT_RX; } static void pl011_write(void *opaque, hwaddr offset, @@ -162,6 +165,10 @@ static void pl011_write(void *opaque, hwaddr offset, s->fbrd = value; break; case 11: /* UARTLCR_H */ + if (!((s->lcr ^ value) & 0x10)) { + s->read_count = 0; + s->read_pos = 0; + } s->lcr = value; pl011_set_read_trigger(s); break; @@ -214,7 +221,7 @@ static void pl011_put_fifo(void *opaque, uint32_t value) s->read_fifo[slot] = value; s->read_count++; s->flags &= ~PL011_FLAG_RXFE; - if (s->cr & 0x10 || s->read_count == 16) { + if (!(s->lcr & 0x10) || s->read_count == 16) { s->flags |= PL011_FLAG_RXFF; } if (s->read_count == s->read_trigger) {