From patchwork Tue Feb 25 14:45:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 25299 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-vc0-f200.google.com (mail-vc0-f200.google.com [209.85.220.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 2FF8320143 for ; Tue, 25 Feb 2014 14:45:54 +0000 (UTC) Received: by mail-vc0-f200.google.com with SMTP id le5sf14651912vcb.7 for ; Tue, 25 Feb 2014 06:45:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=DDshgpbbViQL005uH3kOn28JEZYHsybtgF2U86DGXKA=; b=ZAeje5UPVLATBw4olknbYJiaLZQ2ZcN5ez2i8yMptoRjuPhsIvZFl/VJ5STlk/v6G8 fit9cbUgoTlJEY7UHaZ/uMtIu2bUo2eHW+e3NU9X5FWvcXvC1CQlxrcACUCbONEnXPUA k1Ivg4pmoGLQGD5HE612OHJyz1MHBu+cIUtdwLuat0ITorMbAOmTcSSByUswoMRuO+53 MqziCAd7UkUwojEoAjcEWrdyhTL8UK1t9eD6jNdH+9jFG+nQAF/JOL+PCu+mW77J+6eW bhhZfOuSe0eEF0f5aOIftIvhoqr1NibTjKQVszCKxZoGTIPiK8Snx4dYYMWAv1FJJyB2 Iy1A== X-Gm-Message-State: ALoCoQlPk3LWIOEygjyzvEiVo7BTfdg4P2XMPY73eP31RpFXwFrgXUhStAOa9wrlv0W4QaPPktGN X-Received: by 10.58.46.204 with SMTP id x12mr828945vem.19.1393339553652; Tue, 25 Feb 2014 06:45:53 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.40.11 with SMTP id w11ls2393374qgw.42.gmail; Tue, 25 Feb 2014 06:45:53 -0800 (PST) X-Received: by 10.58.248.5 with SMTP id yi5mr92387vec.42.1393339553410; Tue, 25 Feb 2014 06:45:53 -0800 (PST) Received: from mail-vc0-f182.google.com (mail-vc0-f182.google.com [209.85.220.182]) by mx.google.com with ESMTPS id dq2si6845789veb.69.2014.02.25.06.45.52 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 25 Feb 2014 06:45:53 -0800 (PST) Received-SPF: neutral (google.com: 209.85.220.182 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.182; Received: by mail-vc0-f182.google.com with SMTP id id10so7285514vcb.41 for ; Tue, 25 Feb 2014 06:45:52 -0800 (PST) X-Received: by 10.58.255.233 with SMTP id at9mr1488315ved.20.1393339551634; Tue, 25 Feb 2014 06:45:51 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp144144vcz; Tue, 25 Feb 2014 06:45:48 -0800 (PST) X-Received: by 10.180.7.130 with SMTP id j2mr245543wia.25.1393339547374; Tue, 25 Feb 2014 06:45:47 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id cs3si17958774wjc.60.2014.02.25.06.45.46 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 25 Feb 2014 06:45:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WIJGT-0005l6-C4; Tue, 25 Feb 2014 14:45:45 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Rob Herring , Richard Henderson Subject: [PATCH] target-arm: Implement WFE as a yield operation Date: Tue, 25 Feb 2014 14:45:45 +0000 Message-Id: <1393339545-22111-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.182 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Implement WFE to yield our timeslice to the next CPU. This avoids slowdowns in multicore configurations caused by one core busy-waiting on a spinlock which can't possibly be unlocked until the other core has an opportunity to run. This speeds up my test case A15 dual-core boot by a factor of three (though it is still four or five times slower than a single-core boot). Signed-off-by: Peter Maydell Tested-by: Rob Herring --- RTH pointed out on IRC that we could also implement this by using EXCP_HALTED without setting env->halted; however I think having a separate EXCP_ constant for the yield semantics is less confusing. A full implementation of WFE would be more complicated (there are a lot of conditions which must cause WFE wakeup including SEV from different CPUs and timer event streams), so making it do a yield seems like a useful intermediate fix. This seems to be hugely beneficial on my test case (whereas the recent GIC fix to not accidentally deassert PPIs doesn't have any effect at all). Rob, do you still see things getting worse on your test case with this patch if you have the GIC fix applied too? include/exec/cpu-defs.h | 1 + target-arm/helper.h | 1 + target-arm/op_helper.c | 9 +++++++++ target-arm/translate.c | 6 ++++++ target-arm/translate.h | 2 ++ 5 files changed, 19 insertions(+) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 01cd8c7..66a3d46 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -59,6 +59,7 @@ typedef uint64_t target_ulong; #define EXCP_HLT 0x10001 /* hlt instruction reached */ #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ +#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ #define TB_JMP_CACHE_BITS 12 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) diff --git a/target-arm/helper.h b/target-arm/helper.h index 19bd620..118b425 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -50,6 +50,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(exception, void, env, i32) DEF_HELPER_1(wfi, void, env) +DEF_HELPER_1(wfe, void, env) DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_1(cpsr_read, i32, env) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index eb0fccd..f0e2889 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -225,6 +225,15 @@ void HELPER(wfi)(CPUARMState *env) cpu_loop_exit(env); } +void HELPER(wfe)(CPUARMState *env) +{ + /* Don't actually halt the CPU, just yield back to top + * level loop + */ + env->exception_index = EXCP_YIELD; + cpu_loop_exit(env); +} + void HELPER(exception)(CPUARMState *env, uint32_t excp) { env->exception_index = excp; diff --git a/target-arm/translate.c b/target-arm/translate.c index 6ccf0ba..0c30e5c 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -3939,6 +3939,9 @@ static void gen_nop_hint(DisasContext *s, int val) s->is_jmp = DISAS_WFI; break; case 2: /* wfe */ + gen_set_pc_im(s, s->pc); + s->is_jmp = DISAS_WFE; + break; case 4: /* sev */ case 5: /* sevl */ /* TODO: Implement SEV, SEVL and WFE. May help SMP performance. */ @@ -10801,6 +10804,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, case DISAS_WFI: gen_helper_wfi(cpu_env); break; + case DISAS_WFE: + gen_helper_wfe(cpu_env); + break; case DISAS_SWI: gen_exception(EXCP_SWI); break; diff --git a/target-arm/translate.h b/target-arm/translate.h index 67da699..2f491f9 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -44,6 +44,8 @@ extern TCGv_ptr cpu_env; * emitting unreachable code at the end of the TB in the A64 decoder */ #define DISAS_EXC 6 +/* WFE */ +#define DISAS_WFE 7 #ifdef TARGET_AARCH64 void a64_translate_init(void);