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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id a43si38223336eei.142.2014.02.24.12.24.06 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 24 Feb 2014 12:24:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WI24I-0005P3-4b; Mon, 24 Feb 2014 20:24:02 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexey Kardashevskiy , Evgeny Voevodin , Maksim Kozlov , Igor Mitsyanko , Dmitry Solodkiy , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rob Herring , Peter Crosthwaite Subject: [PATCH 2/4] realview-pbx-a9: Set reset-cbar property for CPUs Date: Mon, 24 Feb 2014 20:24:00 +0000 Message-Id: <1393273442-20736-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1393273442-20736-1-git-send-email-peter.maydell@linaro.org> References: <1393273442-20736-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , If the CPU is a Cortex-A9 then we should set its reset-cbar property so that the guest can read the correct PERIPHBASE/CBAR register value; newer versions of the Linux kernel (as of commit bc41b8724 in 3.12) will otherwise assume the CPU is a buggy single core A9 SoC. The realview-pbx-a9 is the only one of the cluster of boards in realview.c which works with the Cortex-A9 (ie which gets an a9mpcore_priv device); make sure it also has reset-cbar set correctly. Signed-off-by: Peter Maydell --- hw/arm/realview.c | 39 +++++++++++++++++++++++++++++---------- 1 file changed, 29 insertions(+), 10 deletions(-) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 6ef7646..7e04e50 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -18,6 +18,7 @@ #include "hw/i2c/i2c.h" #include "sysemu/blockdev.h" #include "exec/address-spaces.h" +#include "qemu/error-report.h" #define SMP_BOOT_ADDR 0xe0000000 #define SMP_BOOTREG_ADDR 0x10000030 @@ -49,6 +50,7 @@ static void realview_init(QEMUMachineInitArgs *args, { ARMCPU *cpu = NULL; CPUARMState *env; + ObjectClass *cpu_oc; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram_lo = g_new(MemoryRegion, 1); MemoryRegion *ram_hi = g_new(MemoryRegion, 1); @@ -70,12 +72,14 @@ static void realview_init(QEMUMachineInitArgs *args, uint32_t sys_id; ram_addr_t low_ram_size; ram_addr_t ram_size = args->ram_size; + hwaddr periphbase = 0; switch (board_type) { case BOARD_EB: break; case BOARD_EB_MPCORE: is_mpcore = 1; + periphbase = 0x10100000; break; case BOARD_PB_A8: is_pb = 1; @@ -83,16 +87,37 @@ static void realview_init(QEMUMachineInitArgs *args, case BOARD_PBX_A9: is_mpcore = 1; is_pb = 1; + periphbase = 0x1f000000; break; } + + cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, args->cpu_model); + if (!cpu_oc) { + fprintf(stderr, "Unable to find CPU definition\n"); + exit(1); + } + for (n = 0; n < smp_cpus; n++) { - cpu = cpu_arm_init(args->cpu_model); - if (!cpu) { - fprintf(stderr, "Unable to find CPU definition\n"); + Object *cpuobj = object_new(object_class_get_name(cpu_oc)); + Error *err = NULL; + + if (is_pb && is_mpcore) { + object_property_set_int(cpuobj, periphbase, "reset-cbar", &err); + if (err) { + error_report("%s", error_get_pretty(err)); + exit(1); + } + } + + object_property_set_bool(cpuobj, true, "realized", &err); + if (err) { + error_report("%s", error_get_pretty(err)); exit(1); } - cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); + + cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); } + cpu = ARM_CPU(first_cpu); env = &cpu->env; if (arm_feature(env, ARM_FEATURE_V7)) { if (is_mpcore) { @@ -141,16 +166,10 @@ static void realview_init(QEMUMachineInitArgs *args, sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); if (is_mpcore) { - hwaddr periphbase; dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore"); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); qdev_init_nofail(dev); busdev = SYS_BUS_DEVICE(dev); - if (is_pb) { - periphbase = 0x1f000000; - } else { - periphbase = 0x10100000; - } sysbus_mmio_map(busdev, 0, periphbase); for (n = 0; n < smp_cpus; n++) { sysbus_connect_irq(busdev, n, cpu_irq[n]);