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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id ok5si3368674bkb.175.2014.02.21.05.06.49 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 21 Feb 2014 05:06:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WGpoW-00049m-PD; Fri, 21 Feb 2014 13:06:48 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 4/4] hw/arm/musicpal: Avoid shifting left into sign bit Date: Fri, 21 Feb 2014 13:06:48 +0000 Message-Id: <1392988008-15938-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1392988008-15938-1-git-send-email-peter.maydell@linaro.org> References: <1392988008-15938-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.171 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add missing 'U' suffixes to avoid shifting left into sign bit of a signed integer. Signed-off-by: Peter Maydell --- hw/arm/musicpal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 50a3b8f..47e3889 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -112,10 +112,10 @@ #define MP_PHY_88E3015 0x01410E20 /* TX descriptor status */ -#define MP_ETH_TX_OWN (1 << 31) +#define MP_ETH_TX_OWN (1U << 31) /* RX descriptor status */ -#define MP_ETH_RX_OWN (1 << 31) +#define MP_ETH_RX_OWN (1U << 31) /* Interrupt cause/mask bits */ #define MP_ETH_IRQ_RX_BIT 0