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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id mw18si1880042wic.8.2014.02.01.15.00.14 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sat, 01 Feb 2014 15:00:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1W9jXk-0000O7-Cr; Sat, 01 Feb 2014 23:00:08 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Michael Matz , Claudio Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Will Newton , Peter Crosthwaite Subject: [PATCH v2 10/13] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT Date: Sat, 1 Feb 2014 23:00:04 +0000 Message-Id: <1391295607-1426-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1391295607-1426-1-git-send-email-peter.maydell@linaro.org> References: <1391295607-1426-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Implement the 2-reg-misc CNT, NOT and RBIT instructions. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/helper.h | 1 + target-arm/neon_helper.c | 12 ++++++++++++ target-arm/translate-a64.c | 34 ++++++++++++++++++++++++++++------ 3 files changed, 41 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.h b/target-arm/helper.h index 71b8411..951e6ad 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -320,6 +320,7 @@ DEF_HELPER_1(neon_cls_s8, i32, i32) DEF_HELPER_1(neon_cls_s16, i32, i32) DEF_HELPER_1(neon_cls_s32, i32, i32) DEF_HELPER_1(neon_cnt_u8, i32, i32) +DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) diff --git a/target-arm/neon_helper.c b/target-arm/neon_helper.c index be6fbd9..b4c8690 100644 --- a/target-arm/neon_helper.c +++ b/target-arm/neon_helper.c @@ -1133,6 +1133,18 @@ uint32_t HELPER(neon_cnt_u8)(uint32_t x) return x; } +/* Reverse bits in each 8 bit word */ +uint32_t HELPER(neon_rbit_u8)(uint32_t x) +{ + x = ((x & 0xf0f0f0f0) >> 4) + | ((x & 0x0f0f0f0f) << 4); + x = ((x & 0x88888888) >> 3) + | ((x & 0x44444444) >> 1) + | ((x & 0x22222222) << 1) + | ((x & 0x11111111) << 3); + return x; +} + #define NEON_QDMULH16(dest, src1, src2, round) do { \ uint32_t tmp = (int32_t)(int16_t) src1 * (int16_t) src2; \ if ((tmp ^ (tmp << 1)) & SIGNBIT) { \ diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index c071663..dd1bbeb 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -6222,6 +6222,12 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u, TCGCond cond; switch (opcode) { + case 0x5: /* NOT */ + /* This opcode is shared with CNT and RBIT but we have earlier + * enforced that size == 3 if and only if this is the NOT insn. + */ + tcg_gen_not_i64(tcg_rd, tcg_rn); + break; case 0xa: /* CMLT */ /* 64 bit integer comparison against zero, result is * test ? (2^64 - 1) : 0. We implement via setcond(!test) and @@ -7385,13 +7391,19 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x1: /* REV16 */ unsupported_encoding(s, insn); return; - case 0x5: /* CNT, NOT, RBIT */ - if ((u == 0 && size > 0) || - (u == 1 && size > 1)) { - unallocated_encoding(s); - return; + case 0x5: /* CNT, NOT, RBIT */ + if (u && size == 0) { + /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */ + size = 3; + break; + } else if (u && size == 1) { + /* RBIT */ + break; + } else if (!u && size == 0) { + /* CNT */ + break; } - unsupported_encoding(s, insn); + unallocated_encoding(s); return; case 0x2: /* SADDLP, UADDLP */ case 0x4: /* CLS, CLZ */ @@ -7553,6 +7565,16 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } else { /* Use helpers for 8 and 16 bit elements */ switch (opcode) { + case 0x5: /* CNT, RBIT */ + /* For these two insns size is part of the opcode specifier + * (handled earlier); they always operate on byte elements. + */ + if (u) { + gen_helper_neon_rbit_u8(tcg_res, tcg_op); + } else { + gen_helper_neon_cnt_u8(tcg_res, tcg_op); + } + break; case 0x8: /* CMGT, CMGE */ case 0x9: /* CMEQ, CMLE */ case 0xa: /* CMLT */