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[67.169.181.221]) by mx.google.com with ESMTPSA id sq7sm45438283pbc.19.2014.01.28.12.32.52 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 28 Jan 2014 12:32:53 -0800 (PST) From: Christoffer Dall To: qemu-devel@nongnu.org Cc: kvmarm@lists.cs.columbia.edu, patches@linaro.org, Christoffer Dall Subject: [PATCH v5 2/8] arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes Date: Tue, 28 Jan 2014 12:32:39 -0800 Message-Id: <1390941165-2079-3-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.8.5.2 In-Reply-To: <1390941165-2079-1-git-send-email-christoffer.dall@linaro.org> References: <1390941165-2079-1-git-send-email-christoffer.dall@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: christoffer.dall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.182 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Fix two bugs that would allow changing the state of SGIs through the ICPENDR and ISPENDRs. Signed-off-by: Christoffer Dall Reviewed-by: Peter Maydell --- Changes [v1 -> v5]: - New patch in series hw/intc/arm_gic.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 98c6ff5..1c4a114 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -428,7 +428,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, if (irq >= s->num_irq) goto bad_reg; if (irq < GIC_NR_SGIS) { - irq = 0; + value = 0; } for (i = 0; i < 8; i++) { @@ -441,6 +441,10 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; + if (irq < GIC_NR_SGIS) { + value = 0; + } + for (i = 0; i < 8; i++) { /* ??? This currently clears the pending bit for all CPUs, even for per-CPU interrupts. It's unclear whether this is the