From patchwork Sun Jan 26 19:25:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 23712 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-gg0-f200.google.com (mail-gg0-f200.google.com [209.85.161.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 06E06202FA for ; Sun, 26 Jan 2014 19:25:36 +0000 (UTC) Received: by mail-gg0-f200.google.com with SMTP id f4sf7458769ggn.3 for ; Sun, 26 Jan 2014 11:25:36 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=3NlC3bzPUuUeMGP7TJVJRtDE+YD1mjgLqZh1/uEh/Ss=; b=MXyjYkEfbrbJT46sTzzG6j35Y1uf4NikG9+4sgPkN8DzVk04XBxmNhs65IjLnjVX21 af5jJ2r1o07CjN7kgPNFzf55e7aUuFqQpFyb0CTJ0ThNHVFj/G6xS6Siwcea0L2jL+Vo H/a6gNPlFLv8yAbzVCAl4t7vohrRm3HRVu+0gxiSlUvfAS00ObDTZ9CtGpqu0oS18Owj dfcmS0OtnHj2EhXxXNOyhaGfHC5FSg4p04DQ/faa23FOt17a4/63wJIWojsAryoK8QMS og00Co4GS8O4HezKOaXZEfc2WjI60uivDkflzvXTj2Zw6aCl54gPT+f8A8ufdUWWoUMQ vn1w== X-Gm-Message-State: ALoCoQkaBCDm4XOZLzL6RN8rfJqH12SuRJ2L9Hjq2B1MmyBFLZXQV3h5XinyneSV2Eg/jVa6aCRY X-Received: by 10.58.189.73 with SMTP id gg9mr949446vec.34.1390764336026; Sun, 26 Jan 2014 11:25:36 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.48.38 with SMTP id n35ls651913qga.68.gmail; Sun, 26 Jan 2014 11:25:35 -0800 (PST) X-Received: by 10.58.7.1 with SMTP id f1mr13243570vea.15.1390764335905; Sun, 26 Jan 2014 11:25:35 -0800 (PST) Received: from mail-vb0-f41.google.com (mail-vb0-f41.google.com [209.85.212.41]) by mx.google.com with ESMTPS id yv5si4181066veb.140.2014.01.26.11.25.35 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 26 Jan 2014 11:25:35 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.41 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.41; Received: by mail-vb0-f41.google.com with SMTP id g10so2920052vbg.14 for ; Sun, 26 Jan 2014 11:25:35 -0800 (PST) X-Received: by 10.58.181.165 with SMTP id dx5mr13139990vec.19.1390764335826; Sun, 26 Jan 2014 11:25:35 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp81106vcz; Sun, 26 Jan 2014 11:25:35 -0800 (PST) X-Received: by 10.205.102.196 with SMTP id df4mr19591717bkc.2.1390764334761; Sun, 26 Jan 2014 11:25:34 -0800 (PST) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id or7si11365599bkb.74.2014.01.26.11.25.32 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 26 Jan 2014 11:25:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1W7VKT-0005gY-Dz; Sun, 26 Jan 2014 19:25:13 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Michael Matz , Claudio Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Will Newton , Peter Crosthwaite Subject: [PATCH 10/21] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns Date: Sun, 26 Jan 2014 19:25:01 +0000 Message-Id: <1390764312-21789-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1390764312-21789-1-git-send-email-peter.maydell@linaro.org> References: <1390764312-21789-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.41 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Implement the SIMD 3-reg-same instructions where the size == 3 case is reserved: SHADD, UHADD, SRHADD, URHADD, SHSUB, UHSUB, SMAX, UMAX, SMIN, UMIN, SABD, UABD, SABA, UABA, MLA, MLS, MUL, PMUL, SQRDMULH, SQDMULH. (None of these have scalar-3-same versions.) This completes the non-pairwise integer instructions in this category. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 134 +++++++++++++++++++++++++++++++++++++++------ 1 file changed, 118 insertions(+), 16 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 4a6886d..515c72b 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -6684,15 +6684,13 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } - unsupported_encoding(s, insn); - return; + break; case 0x16: /* SQDMULH, SQRDMULH */ if (size == 0 || size == 3) { unallocated_encoding(s); return; } - unsupported_encoding(s, insn); - return; + break; default: if (size == 3 && !is_q) { unallocated_encoding(s); @@ -6730,6 +6728,16 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); switch (opcode) { + case 0x0: /* SHADD, UHADD */ + { + static NeonGenTwoOpFn * const fns[3][2] = { + { gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 }, + { gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 }, + { gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 }, + }; + genfn = fns[size][u]; + break; + } case 0x1: /* SQADD, UQADD */ { static NeonGenTwoOpEnvFn * const fns[3][2] = { @@ -6740,6 +6748,26 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) genenvfn = fns[size][u]; break; } + case 0x2: /* SRHADD, URHADD */ + { + static NeonGenTwoOpFn * const fns[3][2] = { + { gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 }, + { gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 }, + { gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 }, + }; + genfn = fns[size][u]; + break; + } + case 0x4: /* SHSUB, UHSUB */ + { + static NeonGenTwoOpFn * const fns[3][2] = { + { gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 }, + { gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 }, + { gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 }, + }; + genfn = fns[size][u]; + break; + } case 0x5: /* SQSUB, UQSUB */ { static NeonGenTwoOpEnvFn * const fns[3][2] = { @@ -6773,9 +6801,9 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) case 0x8: /* SSHL, USHL */ { static NeonGenTwoOpFn * const fns[3][2] = { - { gen_helper_neon_shl_u8, gen_helper_neon_shl_s8 }, - { gen_helper_neon_shl_u16, gen_helper_neon_shl_s16 }, - { gen_helper_neon_shl_u32, gen_helper_neon_shl_s32 }, + { gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 }, + { gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 }, + { gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 }, }; genfn = fns[size][u]; break; @@ -6783,9 +6811,9 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) case 0x9: /* SQSHL, UQSHL */ { static NeonGenTwoOpEnvFn * const fns[3][2] = { - { gen_helper_neon_qshl_u8, gen_helper_neon_qshl_s8 }, - { gen_helper_neon_qshl_u16, gen_helper_neon_qshl_s16 }, - { gen_helper_neon_qshl_u32, gen_helper_neon_qshl_s32 }, + { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, + { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, + { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, }; genenvfn = fns[size][u]; break; @@ -6793,9 +6821,9 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) case 0xa: /* SRSHL, URSHL */ { static NeonGenTwoOpFn * const fns[3][2] = { - { gen_helper_neon_rshl_u8, gen_helper_neon_rshl_s8 }, - { gen_helper_neon_rshl_u16, gen_helper_neon_rshl_s16 }, - { gen_helper_neon_rshl_u32, gen_helper_neon_rshl_s32 }, + { gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 }, + { gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 }, + { gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 }, }; genfn = fns[size][u]; break; @@ -6803,13 +6831,45 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) case 0xb: /* SQRSHL, UQRSHL */ { static NeonGenTwoOpEnvFn * const fns[3][2] = { - { gen_helper_neon_qrshl_u8, gen_helper_neon_qrshl_s8 }, - { gen_helper_neon_qrshl_u16, gen_helper_neon_qrshl_s16 }, - { gen_helper_neon_qrshl_u32, gen_helper_neon_qrshl_s32 }, + { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, + { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, + { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, }; genenvfn = fns[size][u]; break; } + case 0xc: /* SMAX, UMAX */ + { + static NeonGenTwoOpFn * const fns[3][2] = { + { gen_helper_neon_max_s8, gen_helper_neon_max_u8 }, + { gen_helper_neon_max_s16, gen_helper_neon_max_u16 }, + { gen_helper_neon_max_s32, gen_helper_neon_max_u32 }, + }; + genfn = fns[size][u]; + break; + } + + case 0xd: /* SMIN, UMIN */ + { + static NeonGenTwoOpFn * const fns[3][2] = { + { gen_helper_neon_min_s8, gen_helper_neon_min_u8 }, + { gen_helper_neon_min_s16, gen_helper_neon_min_u16 }, + { gen_helper_neon_min_s32, gen_helper_neon_min_u32 }, + }; + genfn = fns[size][u]; + break; + } + case 0xe: /* SABD, UABD */ + case 0xf: /* SABA, UABA */ + { + static NeonGenTwoOpFn * const fns[3][2] = { + { gen_helper_neon_abd_s8, gen_helper_neon_abd_u8 }, + { gen_helper_neon_abd_s16, gen_helper_neon_abd_u16 }, + { gen_helper_neon_abd_s32, gen_helper_neon_abd_u32 }, + }; + genfn = fns[size][u]; + break; + } case 0x10: /* ADD, SUB */ { static NeonGenTwoOpFn * const fns[3][2] = { @@ -6830,6 +6890,34 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) genfn = fns[size][u]; break; } + case 0x13: /* MUL, PMUL */ + if (u) { + /* PMUL */ + assert(size == 0); + genfn = gen_helper_neon_mul_p8; + break; + } + /* fall through : MUL */ + case 0x12: /* MLA, MLS */ + { + static NeonGenTwoOpFn * const fns[3] = { + gen_helper_neon_mul_u8, + gen_helper_neon_mul_u16, + tcg_gen_mul_i32, + }; + genfn = fns[size]; + break; + } + case 0x16: /* SQDMULH, SQRDMULH */ + { + static NeonGenTwoOpEnvFn * const fns[2][2] = { + { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, + { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, + }; + assert(size == 1 || size == 2); + genenvfn = fns[size - 1][u]; + break; + } default: g_assert_not_reached(); } @@ -6840,6 +6928,20 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) genfn(tcg_res, tcg_op1, tcg_op2); } + if (opcode == 0xf || opcode == 0x12) { + /* SABA, UABA, MLA, MLS: accumulating ops */ + static NeonGenTwoOpFn * const fns[3][2] = { + { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, + { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, + { tcg_gen_add_i32, tcg_gen_sub_i32 }, + }; + bool is_sub = (opcode == 0x12 && u); /* MLS */ + + genfn = fns[size][is_sub]; + read_vec_element_i32(s, tcg_op1, rd, pass, MO_32); + genfn(tcg_res, tcg_res, tcg_op1); + } + write_vec_element_i32(s, tcg_res, rd, pass, MO_32); tcg_temp_free_i32(tcg_res);