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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id r2si4397018wic.62.2014.01.21.12.27.19 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 21 Jan 2014 12:27:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1W5hgV-0003Wd-IF; Tue, 21 Jan 2014 20:12:31 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Michael Matz , Claudio Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Will Newton , Peter Crosthwaite Subject: [PATCH 14/24] target-arm: Implement AArch64 dummy MDSCR_EL1 Date: Tue, 21 Jan 2014 20:12:20 +0000 Message-Id: <1390335150-13470-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1390335150-13470-1-git-send-email-peter.maydell@linaro.org> References: <1390335150-13470-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , We don't support letting the guest do debug, but Linux prods the monitor debug system control register anyway, so implement a dummy RAZ/WI version. --- target-arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index ffe245f..69cce6f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1761,6 +1761,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7, .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = tlbi_aa64_vaa_write }, + /* Dummy implementation of monitor debug system control register: + * we don't support debug. + */ + { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, REGINFO_SENTINEL };