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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id o17si2480545wie.52.2014.01.21.12.12.37 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 21 Jan 2014 12:12:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1W5hgV-0003WR-CA; Tue, 21 Jan 2014 20:12:31 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Michael Matz , Claudio Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Will Newton , Peter Crosthwaite Subject: [PATCH 11/24] target-arm: Implement AArch64 DAIF system register Date: Tue, 21 Jan 2014 20:12:17 +0000 Message-Id: <1390335150-13470-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1390335150-13470-1-git-send-email-peter.maydell@linaro.org> References: <1390335150-13470-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Implement the DAIF system register which is a view of the DAIF bits in PSTATE. TODO: include support for the MSR_i encodings? Signed-off-by: Peter Maydell --- target-arm/helper.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 51b71a4..f23b500 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1590,6 +1590,27 @@ static int aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, return 0; } +static int aa64_daif_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t *value) +{ + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) { + return EXCP_UDEF; + } + *value = pstate_read(env) & PSTATE_DAIF; + return 0; +} + +static int aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) { + return EXCP_UDEF; + } + env->pstate &= ~PSTATE_DAIF; + env->pstate |= (value & PSTATE_DAIF); + return 0; +} + static const ARMCPRegInfo v8_cp_reginfo[] = { /* Minimal set of EL0-visible registers. This will need to be expanded * significantly for system emulation of AArch64 CPUs. @@ -1597,6 +1618,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "NZCV", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, .access = PL0_RW, .type = ARM_CP_NZCV }, + { .name = "DAIF", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, + .access = PL0_RW, .type = ARM_CP_NO_MIGRATE, + .readfn = aa64_daif_read, .writefn = aa64_daif_write }, { .name = "FPCR", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },