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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id oo9si2357428wjc.31.2013.12.30.08.34.39 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 30 Dec 2013 08:34:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1VxfnX-0000XM-Rm; Mon, 30 Dec 2013 16:34:35 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Michael Matz , Claudio Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Will Newton , Peter Crosthwaite Subject: [PATCH v2 01/10] target-arm: A64: Add support for dumping AArch64 VFP register state Date: Mon, 30 Dec 2013 16:34:26 +0000 Message-Id: <1388421275-2035-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1388421275-2035-1-git-send-email-peter.maydell@linaro.org> References: <1388421275-2035-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.52 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Alexander Graf When dumping the current CPU state, we can also get a request to dump the FPU state along with the CPU's integer state. Add support to dump the VFP state when that flag is set, so that we can properly debug code that modifies floating point registers. Signed-off-by: Alexander Graf [WN: Commit message tweak, rebased. Output all registers, two per-line.] Signed-off-by: Will Newton Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 40c6fc4..326f36d 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -119,6 +119,22 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, psr & PSTATE_C ? 'C' : '-', psr & PSTATE_V ? 'V' : '-'); cpu_fprintf(f, "\n"); + + if (flags & CPU_DUMP_FPU) { + int numvfpregs = 32; + for (i = 0; i < numvfpregs; i += 2) { + uint64_t vlo = float64_val(env->vfp.regs[i * 2]); + uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]); + cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ", + i, vhi, vlo); + vlo = float64_val(env->vfp.regs[(i + 1) * 2]); + vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]); + cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n", + i + 1, vhi, vlo); + } + cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n", + vfp_get_fpcr(env), vfp_get_fpsr(env)); + } } static int get_mem_index(DisasContext *s)