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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id l2si6618214wiy.3.2013.12.09.04.37.37 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 09 Dec 2013 04:37:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Vq05e-00006n-Hv; Mon, 09 Dec 2013 12:37:34 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Will Newton Subject: [PATCH v3 07/13] target-arm: A64: add support for 1-src data processing and CLZ Date: Mon, 9 Dec 2013 12:37:28 +0000 Message-Id: <1386592654-362-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386592654-362-1-git-send-email-peter.maydell@linaro.org> References: <1386592654-362-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Claudio Fontana This patch adds support for decoding 1-src data processing insns, and the first user, C5.6.40 CLZ (count leading zeroes). Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/helper-a64.c | 5 +++++ target-arm/helper-a64.h | 1 + target-arm/translate-a64.c | 52 ++++++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 56 insertions(+), 2 deletions(-) diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index abb98c0..e4c5346 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -44,3 +44,8 @@ int64_t HELPER(sdiv64)(int64_t num, int64_t den) } return num / den; } + +uint64_t HELPER(clz64)(uint64_t x) +{ + return clz64(x); +} diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h index e0d6506..b10b6c3 100644 --- a/target-arm/helper-a64.h +++ b/target-arm/helper-a64.h @@ -18,3 +18,4 @@ */ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) +DEF_HELPER_FLAGS_1(clz64, TCG_CALL_NO_RWG_SE, i64, i64) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 2f673d6..908afcd 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1044,10 +1044,58 @@ static void disas_cond_select(DisasContext *s, uint32_t insn) } } -/* Data-processing (1 source) */ +static void handle_clz(DisasContext *s, unsigned int sf, + unsigned int rn, unsigned int rd) +{ + TCGv_i64 tcg_rd, tcg_rn; + tcg_rd = cpu_reg(s, rd); + tcg_rn = cpu_reg(s, rn); + + if (sf) { + gen_helper_clz64(tcg_rd, tcg_rn); + } else { + TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); + tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); + gen_helper_clz(tcg_tmp32, tcg_tmp32); + tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); + tcg_temp_free_i32(tcg_tmp32); + } +} + +/* C3.5.7 Data-processing (1 source) + * 31 30 29 28 21 20 16 15 10 9 5 4 0 + * +----+---+---+-----------------+---------+--------+------+------+ + * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd | + * +----+---+---+-----------------+---------+--------+------+------+ + */ static void disas_data_proc_1src(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + unsigned int sf, opcode, rn, rd; + + if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) { + unallocated_encoding(s); + return; + } + + sf = extract32(insn, 31, 1); + opcode = extract32(insn, 10, 6); + rn = extract32(insn, 5, 5); + rd = extract32(insn, 0, 5); + + switch (opcode) { + case 0: /* RBIT */ + case 1: /* REV16 */ + case 2: /* REV32 */ + case 3: /* REV64 */ + unsupported_encoding(s, insn); + break; + case 4: /* CLZ */ + handle_clz(s, sf, rn, rd); + break; + case 5: /* CLS */ + unsupported_encoding(s, insn); + break; + } } static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,