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[81.2.115.146]) by mx.google.com with ESMTPS id 8si7223299pbe.70.2013.12.09.04.37.38 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 09 Dec 2013 04:37:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Vq05e-00006V-9m; Mon, 09 Dec 2013 12:37:34 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Will Newton Subject: [PATCH v3 03/13] target-arm: A64: add support for ADR and ADRP Date: Mon, 9 Dec 2013 12:37:24 +0000 Message-Id: <1386592654-362-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386592654-362-1-git-send-email-peter.maydell@linaro.org> References: <1386592654-362-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Alexander Graf Add support for the instructions described in "C3.4.6 PC-rel. addressing" (ADR and ADRP). Signed-off-by: Alexander Graf [claudio: adapted to new decoder structure] Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson --- target-arm/translate-a64.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 6d42177..9e11621 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -653,10 +653,31 @@ static void disas_ldst(DisasContext *s, uint32_t insn) } } -/* PC-rel. addressing */ +/* C3.4.6 PC-rel. addressing + * 31 30 29 28 24 23 5 4 0 + * +----+-------+-----------+-------------------+------+ + * | op | immlo | 1 0 0 0 0 | immhi | Rd | + * +----+-------+-----------+-------------------+------+ + */ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + unsigned int page, rd; + uint64_t base; + int64_t offset; + + page = extract32(insn, 31, 1); + /* SignExtend(immhi:immlo) -> offset */ + offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2); + rd = extract32(insn, 0, 5); + base = s->pc - 4; + + if (page) { + /* ADRP (page based) */ + base &= ~0xfff; + offset <<= 12; + } + + tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); } /* Add/subtract (immediate) */