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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id kq2si36558969wjc.87.2013.12.06.05.19.41 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 06 Dec 2013 05:19:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1VovJJ-0007Wz-Tv; Fri, 06 Dec 2013 13:19:13 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Will Newton Subject: [PATCH v2 12/13] target-arm: A64: add support for 1-src CLS insn Date: Fri, 6 Dec 2013 13:19:12 +0000 Message-Id: <1386335953-28876-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386335953-28876-1-git-send-email-peter.maydell@linaro.org> References: <1386335953-28876-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.178 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Claudio Fontana this patch adds support for the CLS instruction. Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/helper-a64.c | 10 ++++++++++ target-arm/helper-a64.h | 2 ++ target-arm/translate-a64.c | 20 +++++++++++++++++++- 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index cccaac6..d3f7067 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -50,6 +50,16 @@ uint64_t HELPER(clz64)(uint64_t x) return clz64(x); } +uint64_t HELPER(cls64)(uint64_t x) +{ + return clrsb64(x); +} + +uint32_t HELPER(cls32)(uint32_t x) +{ + return clrsb32(x); +} + uint64_t HELPER(rbit64)(uint64_t x) { /* assign the correct byte position */ diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h index 9959139..a163a94 100644 --- a/target-arm/helper-a64.h +++ b/target-arm/helper-a64.h @@ -19,4 +19,6 @@ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_1(clz64, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_FLAGS_1(cls64, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_FLAGS_1(cls32, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index ee2ecb4..3d289d5 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1106,6 +1106,24 @@ static void handle_clz(DisasContext *s, unsigned int sf, } } +static void handle_cls(DisasContext *s, unsigned int sf, + unsigned int rn, unsigned int rd) +{ + TCGv_i64 tcg_rd, tcg_rn; + tcg_rd = cpu_reg(s, rd); + tcg_rn = cpu_reg(s, rn); + + if (sf) { + gen_helper_cls64(tcg_rd, tcg_rn); + } else { + TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); + tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); + gen_helper_cls32(tcg_tmp32, tcg_tmp32); + tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); + tcg_temp_free_i32(tcg_tmp32); + } +} + static void handle_rbit(DisasContext *s, unsigned int sf, unsigned int rn, unsigned int rd) { @@ -1228,7 +1246,7 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn) handle_clz(s, sf, rn, rd); break; case 5: /* CLS */ - unsupported_encoding(s, insn); + handle_cls(s, sf, rn, rd); break; } }