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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id lh14si12803wic.63.2013.12.05.13.51.52 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 05 Dec 2013 13:51:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1VogpV-0007CH-At; Thu, 05 Dec 2013 21:51:29 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christoffer Dall , Will Newton Subject: [PATCH 01/13] target-arm: A64: add support for conditional select Date: Thu, 5 Dec 2013 21:51:17 +0000 Message-Id: <1386280289-27636-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386280289-27636-1-git-send-email-peter.maydell@linaro.org> References: <1386280289-27636-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Claudio Fontana This patch adds support for the instruction group "C3.5.6 Conditional select": CSEL, CSINC, CSINV, CSNEG. Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 56 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index fdc3ed8..a9c1803 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -724,10 +724,62 @@ static void disas_cc_reg(DisasContext *s, uint32_t insn) unsupported_encoding(s, insn); } -/* Conditional select */ +/* C3.5.6 Conditional select + * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0 + * +----+----+---+-----------------+------+------+-----+------+------+ + * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd | + * +----+----+---+-----------------+------+------+-----+------+------+ + */ static void disas_cond_select(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + unsigned int sf, else_inv, rm, cond, else_inc, rn, rd; + TCGv_i64 tcg_rd, tcg_src; + + if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { + /* S == 1 or op2<1> == 1 */ + unallocated_encoding(s); + return; + } + sf = extract32(insn, 31, 1); + else_inv = extract32(insn, 30, 1); + rm = extract32(insn, 16, 5); + cond = extract32(insn, 12, 4); + else_inc = extract32(insn, 10, 1); + rn = extract32(insn, 5, 5); + rd = extract32(insn, 0, 5); + tcg_rd = cpu_reg(s, rd); + + if (cond >= 0x0e) { /* condition "always" */ + tcg_src = read_cpu_reg(s, rn, sf); + tcg_gen_mov_i64(tcg_rd, tcg_src); + } else { + /* OPTME: we could use movcond here, at the cost of duplicating + * a lot of the arm_gen_test_cc() logic. + */ + int label_match = gen_new_label(); + int label_continue = gen_new_label(); + + arm_gen_test_cc(cond, label_match); + /* nomatch: */ + tcg_src = read_cpu_reg(s, rm, sf); + tcg_gen_mov_i64(tcg_rd, tcg_src); + if (else_inv) { + tcg_gen_not_i64(tcg_rd, tcg_rd); + } + if (else_inc) { + tcg_gen_addi_i64(tcg_rd, tcg_rd, 1); + } + if (!sf) { + tcg_gen_ext32u_i64(tcg_rd, tcg_rd); + } + tcg_gen_br(label_continue); + /* match: */ + gen_set_label(label_match); + tcg_src = read_cpu_reg(s, rn, sf); + tcg_gen_mov_i64(tcg_rd, tcg_src); + /* continue: */ + gen_set_label(label_continue); + } } /* Data-processing (1 source) */