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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id o6si998720wia.77.2013.12.05.04.39.44 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 05 Dec 2013 04:39:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1VoYDU-00071z-PW; Thu, 05 Dec 2013 12:39:40 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , C Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v3 02/12] target-arm: A64: add set_pc cpu method Date: Thu, 5 Dec 2013 12:39:30 +0000 Message-Id: <1386247180-26994-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386247180-26994-1-git-send-email-peter.maydell@linaro.org> References: <1386247180-26994-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Alexander Graf When executing translation blocks we need to be able to recover our program counter. Add a method to set it for AArch64 CPUs. This covers user-mode, but for system mode emulation we will need to check if the CPU is in an AArch32 execution state. Signed-off-by: Alexander Graf Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/cpu64.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index 3e99c21..04ce879 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -68,11 +68,22 @@ static void aarch64_cpu_finalizefn(Object *obj) { } +static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) +{ + ARMCPU *cpu = ARM_CPU(cs); + /* + * TODO: this will need updating for system emulation, + * when the core may be in AArch32 mode. + */ + cpu->env.pc = value; +} + static void aarch64_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); cc->dump_state = aarch64_cpu_dump_state; + cc->set_pc = aarch64_cpu_set_pc; cc->gdb_read_register = aarch64_cpu_gdb_read_register; cc->gdb_write_register = aarch64_cpu_gdb_write_register; cc->gdb_num_core_regs = 34;