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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id bo12si1722094wib.66.2013.12.04.11.33.34 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 04 Dec 2013 11:33:35 -0800 (PST) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1VoICP-0006eY-Ka; Wed, 04 Dec 2013 19:33:29 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , C Fontana , Dirk Mueller , Michael Matz , Laurent Desnogues , Richard Henderson , kvmarm@lists.cs.columbia.edu Subject: [PATCH v2 11/12] target-arm: A64: add support for 'test and branch' imm Date: Wed, 4 Dec 2013 19:33:28 +0000 Message-Id: <1386185609-25505-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386185609-25505-1-git-send-email-peter.maydell@linaro.org> References: <1386185609-25505-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Alexander Graf This patch adds emulation for the test and branch insns, TBZ and TBNZ. Signed-off-by: Alexander Graf [claudio: adapted for new decoder always compare with 0 remove a TCG temporary ] Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/translate-a64.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index afad874..b79672b 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -215,10 +215,33 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) unsupported_encoding(s, insn); } -/* Test & branch (immediate) */ +/* C3.2.5 Test & branch (immediate) + * 31 30 25 24 23 19 18 5 4 0 + * +----+-------------+----+-------+-------------+------+ + * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | + * +----+-------------+----+-------+-------------+------+ + */ static void disas_test_b_imm(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + unsigned int bit_pos, op, rt; + uint64_t addr; + int label_match; + TCGv_i64 tcg_cmp; + + bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); + op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ + addr = s->pc + sextract32(insn, 5, 14) * 4 - 4; + rt = extract32(insn, 0, 5); + + tcg_cmp = tcg_temp_new_i64(); + tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); + label_match = gen_new_label(); + tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, + tcg_cmp, 0, label_match); + tcg_temp_free_i64(tcg_cmp); + gen_goto_tb(s, 0, s->pc); + gen_set_label(label_match); + gen_goto_tb(s, 1, addr); } /* C3.2.2 / C5.6.19 Conditional branch (immediate)