From patchwork Tue Dec 3 21:51:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 22003 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-vc0-f198.google.com (mail-vc0-f198.google.com [209.85.220.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 5B65D202DA for ; Tue, 3 Dec 2013 21:52:36 +0000 (UTC) Received: by mail-vc0-f198.google.com with SMTP id ld13sf32738289vcb.5 for ; Tue, 03 Dec 2013 13:52:36 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=ZbgdmeQcXRk8mwhQ5NGl69SHg/98nA8vY/eNXaJuGWA=; b=f4hNiAa7sqho4jI1NUh3ATD5Cr+ZHvp5QO1z8r8ltGx+lXM2G1lTJS8sY1yKMoFC/M xJlbTltJ0h1OhjHy41d/inqu+sdNMfvEbnRw3VS4k4UKqSM/Kl/CaoBN6+nNLjxPlABI TY3WWRVshkivYroxZC5SUaLEroY98GQt0udAS3tG+2HKEbwwUBmib6lK3D45Qpr2hMtT OvENPyI/UwZtw9724ODAQFCPyLvUZypoI9J/kem8Dd7HZeUIC7hyt/p51eFwr172Cil7 GeMwJfTMCCPJTcdx8YT8cOfDu+ZnIHvHhatJB2J8PDxP9XAKPoWh39Me8YrBnvKPCUAE ViYA== X-Gm-Message-State: ALoCoQn3yxpOQWiea6+n9oqAGB4F84L/yLRILHKcXpY4wbpp5IMZ1oBHiwCKqcArrKuCB3hURpXI X-Received: by 10.58.76.129 with SMTP id k1mr24912699vew.19.1386107556158; Tue, 03 Dec 2013 13:52:36 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.48.129 with SMTP id l1ls1866qen.75.gmail; Tue, 03 Dec 2013 13:52:36 -0800 (PST) X-Received: by 10.58.255.233 with SMTP id at9mr7158942ved.20.1386107556006; Tue, 03 Dec 2013 13:52:36 -0800 (PST) Received: from mail-ve0-f173.google.com (mail-ve0-f173.google.com [209.85.128.173]) by mx.google.com with ESMTPS id z17si20117593vcy.83.2013.12.03.13.52.35 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 03 Dec 2013 13:52:36 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.173; Received: by mail-ve0-f173.google.com with SMTP id oz11so10848128veb.4 for ; Tue, 03 Dec 2013 13:52:35 -0800 (PST) X-Received: by 10.58.210.66 with SMTP id ms2mr57962523vec.10.1386107555808; Tue, 03 Dec 2013 13:52:35 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp243348vcz; Tue, 3 Dec 2013 13:52:35 -0800 (PST) X-Received: by 10.180.160.239 with SMTP id xn15mr4448005wib.17.1386107554307; Tue, 03 Dec 2013 13:52:34 -0800 (PST) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id d8si116323wiv.76.2013.12.03.13.52.33 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 03 Dec 2013 13:52:34 -0800 (PST) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1VnxsD-0006Ik-Fa; Tue, 03 Dec 2013 21:51:17 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , C Fontana , Dirk Mueller , Michael Matz , Laurent Desnogues , Richard Henderson , kvmarm@lists.cs.columbia.edu Subject: [PATCH 08/12] target-arm: A64: add support for B and BL insns Date: Tue, 3 Dec 2013 21:51:13 +0000 Message-Id: <1386107477-24165-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386107477-24165-1-git-send-email-peter.maydell@linaro.org> References: <1386107477-24165-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Alexander Graf Implement the B and BL instructions (PC relative branches and calls). For convenience in managing TCG temporaries which might be generated if a source register is the zero-register XZR, we provide a simple mechanism for creating a new temp which is automatically freed at the end of decode of the instruction. Signed-off-by: Alexander Graf [claudio: renamed functions, adapted to new decoder layout] Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 45 ++++++++++++++++++++++++++++++++++++++++++-- target-arm/translate.h | 3 +++ 2 files changed, 46 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 29f001d..8535803 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -160,16 +160,53 @@ static void unallocated_encoding(DisasContext *s) unallocated_encoding(s); \ } while (0); +static void free_tmp_a64(DisasContext *s) +{ + int i; + for (i = 0; i < s->tmp_a64_count; i++) { + tcg_temp_free_i64(s->tmp_a64[i]); + } + s->tmp_a64_count = 0; +} + +static TCGv_i64 new_tmp_a64_zero(DisasContext *s) +{ + assert(s->tmp_a64_count < TMP_A64_MAX); + return s->tmp_a64[s->tmp_a64_count++] = tcg_const_i64(0); +} + +static TCGv_i64 cpu_reg(DisasContext *s, int reg) +{ + if (reg == 31) { + return new_tmp_a64_zero(s); + } else { + return cpu_X[reg]; + } +} + /* * the instruction disassembly implemented here matches * the instruction encoding classifications in chapter 3 (C3) * of the ARM Architecture Reference Manual (DDI0487A_a) */ -/* Unconditional branch (immediate) */ +/* C3.2.7 Unconditional branch (immediate) + * 31 30 26 25 0 + * +----+-----------+-------------------------------------+ + * | op | 0 0 1 0 1 | imm26 | + * +----+-----------+-------------------------------------+ + */ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4; + + if (insn & (1 << 31)) { + /* C5.6.26 BL Branch with link */ + tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); + } + + /* C5.6.20 B Branch / C5.6.26 BL Branch with link */ + gen_goto_tb(s, 0, addr); } /* Compare & branch (immediate) */ @@ -650,6 +687,9 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) assert(FALSE); /* all 15 cases should be handled above */ break; } + + /* if we allocated any temporaries, free them here */ + free_tmp_a64(s); } void gen_intermediate_code_internal_a64(ARMCPU *cpu, @@ -679,6 +719,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, dc->condjmp = 0; dc->aarch64 = 1; + dc->tmp_a64_count = 0; dc->thumb = 0; dc->bswap_code = 0; dc->condexec_mask = 0; diff --git a/target-arm/translate.h b/target-arm/translate.h index 8789181..23a45da 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -24,6 +24,9 @@ typedef struct DisasContext { int vec_len; int vec_stride; int aarch64; +#define TMP_A64_MAX 16 + int tmp_a64_count; + TCGv_i64 tmp_a64[TMP_A64_MAX]; } DisasContext; extern TCGv_ptr cpu_env;