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[81.2.115.146]) by mx.google.com with ESMTPS id k8si16184651lag.64.2013.12.03.13.51.21 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 03 Dec 2013 13:51:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1VnxsD-0006IQ-8t; Tue, 03 Dec 2013 21:51:17 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , C Fontana , Dirk Mueller , Michael Matz , Laurent Desnogues , Richard Henderson , kvmarm@lists.cs.columbia.edu Subject: [PATCH 03/12] target-arm: A64: provide functions for accessing FPCR and FPSR Date: Tue, 3 Dec 2013 21:51:08 +0000 Message-Id: <1386107477-24165-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386107477-24165-1-git-send-email-peter.maydell@linaro.org> References: <1386107477-24165-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.169 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The information which AArch32 holds in the FPSCR is split for AArch64 into two logically distinct registers, FPSR and FPCR. Since they are carefully arranged to use non-overlapping bits, we leave the underlying state in the same place, and provide accessor functions which just update the appropriate bits via vfp_get_fpscr() and vfp_set_fpscr(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/cpu.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index ff7aac5..4807354 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -445,6 +445,34 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); +/* For A64 the FPSCR is split into two logically distinct registers, + * FPCR and FPSR. However since they still use non-overlapping bits + * we store the underlying state in fpscr and just mask on read/write. + */ +#define FPSR_MASK 0xf800009f +#define FPCR_MASK 0x07f79f00 +static inline uint32_t vfp_get_fpsr(CPUARMState *env) +{ + return vfp_get_fpscr(env) & FPSR_MASK; +} + +static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) +{ + uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); + vfp_set_fpscr(env, new_fpscr); +} + +static inline uint32_t vfp_get_fpcr(CPUARMState *env) +{ + return vfp_get_fpscr(env) & FPCR_MASK; +} + +static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) +{ + uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); + vfp_set_fpscr(env, new_fpscr); +} + enum arm_cpu_mode { ARM_CPU_MODE_USR = 0x10, ARM_CPU_MODE_FIQ = 0x11,